| Line 28... |
Line 28... |
-- Notes : Requires an externally provided uSec tick input - one clock
|
-- Notes : Requires an externally provided uSec tick input - one clock
|
-- : per microsecond.
|
-- : per microsecond.
|
--
|
--
|
-- Register Map:
|
-- Register Map:
|
-- Offset Bitfield Description Read/Write
|
-- Offset Bitfield Description Read/Write
|
-- 0x0 AAAAAAAA B0 of Setpoint (W) or Buffered Time(R)
|
-- 0x0 AAAAAAAA B0 of Buffered Setpoint (W) or Current Setpoint(R)
|
-- 0x1 AAAAAAAA B1 of Setpoint (W) or Buffered Time(R)
|
-- 0x1 AAAAAAAA B1 of Buffered Setpoint (W) or Current Setpoint(R)
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-- 0x2 AAAAAAAA B2 of Setpoint (W) or Buffered Time(R)
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-- 0x2 AAAAAAAA B2 of Buffered Setpoint (W) or Current Setpoint(R)
|
-- 0x3 C-----BA Control/Status register (RW)
|
-- 0x3 BA------ Status of buffer/alarm (1 = pending, 0 = current)
|
-- A = Update Buffered Time from internal timer (W)
|
-- A = Pending status (R)
|
-- B = Reset Internal Epoch Time (W)
|
-- B = Alarm status (R)
|
-- C = Alarm State Flag (RW) (write a 1 to clear)
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-- Note that any write will update the internal set point
|
|
-- and clear the alarm
|
|
-- 0x4 AAAAAAAA B0 of Current Epoch Time(RO)
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-- 0x5 AAAAAAAA B1 of Current Epoch Time(RO)
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-- 0x6 AAAAAAAA B2 of Current Epoch Time(RO)
|
|
-- Note that any write to 0x04,0x05, or 0x06 will copy the
|
|
-- current epoch time to a readable output buffer
|
|
-- 0x7 -------- Epoch Time Latch/Clear Control Register
|
|
-- Any write to 0x7 will clear/reset the timer and compare val
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 07/28/11 Design Start
|
-- Seth Henry 07/28/11 Design Start
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| Line 72... |
Line 80... |
);
|
);
|
end entity;
|
end entity;
|
|
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architecture behave of o8_epoch_timer is
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architecture behave of o8_epoch_timer is
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|
|
constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 3)
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:= Address(15 downto 2);
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:= Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 3);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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|
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(1 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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|
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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|
|
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signal setpt_buffer : std_logic_vector(23 downto 0) := (others => '0');
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alias setpt_buffer_b0 is setpt_buffer(7 downto 0);
|
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alias setpt_buffer_b1 is setpt_buffer(15 downto 8);
|
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alias setpt_buffer_b2 is setpt_buffer(23 downto 16);
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|
|
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signal epoch_buffer : std_logic_vector(23 downto 0) := (others => '0');
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alias epoch_buffer_b0 is epoch_buffer(7 downto 0);
|
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alias epoch_buffer_b1 is epoch_buffer(15 downto 8);
|
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alias epoch_buffer_b2 is epoch_buffer(23 downto 16);
|
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signal buffer_pending : std_logic := '0';
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signal buffer_update : std_logic := '0';
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signal timer_clear : std_logic := '0';
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|
|
signal epoch_tmr : std_logic_vector(25 downto 0);
|
signal epoch_tmr : std_logic_vector(25 downto 0) := (others => '0');
|
alias epoch_tmrcmp is epoch_tmr(25 downto 2);
|
alias epoch_tmrcmp is epoch_tmr(25 downto 2);
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signal epoch_buffer : std_logic_vector(23 downto 0);
|
signal epoch_setpt : std_logic_vector(25 downto 0) := (others => '0');
|
signal epoch_setpt : std_logic_vector(25 downto 0);
|
alias epoch_setpt_b0 is epoch_setpt(7 downto 0);
|
signal epoch_alarm : std_logic;
|
alias epoch_setpt_b1 is epoch_setpt(15 downto 8);
|
signal epoch_alarm_q : std_logic;
|
alias epoch_setpt_b2 is epoch_setpt(23 downto 16);
|
|
alias epoch_setpt_u is epoch_setpt(25 downto 2);
|
|
alias epoch_setpt_l is epoch_setpt(1 downto 0);
|
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signal epoch_alarm : std_logic := '0';
|
|
signal epoch_alarm_q : std_logic := '0';
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
epoch_tmr <= (others => '0');
|
|
epoch_buffer <= (others => '0');
|
|
epoch_setpt <= (others => '0');
|
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epoch_alarm <= '0';
|
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epoch_alarm_q <= '0';
|
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Wr_Data_q <= (others => '0');
|
Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
|
Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
|
Wr_En <= '0';
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Interrupt <= '0';
|
setpt_buffer <= (others => '0');
|
|
epoch_buffer <= (others => '0');
|
|
buffer_pending <= '0';
|
|
buffer_update <= '0';
|
|
timer_clear <= '0';
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
epoch_tmr <= epoch_tmr + uSec_Tick;
|
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
|
-- reduced to 1uS (reproducing the original behavior). Software should
|
|
-- always subtract 4uS (-1) from the desired time to compensate
|
|
epoch_setpt(1 downto 0) <= "11";
|
|
if( epoch_setpt(25 downto 2) = 0 )then
|
|
epoch_setpt(1 downto 0) <= "00";
|
|
end if;
|
|
|
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Addr_q <= Reg_Addr;
|
Wr_Data_q <= Wr_Data;
|
|
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
if( Wr_En = '1' and or_reduce(Reg_Addr_q) = '0' )then
|
Wr_Data_q <= Wr_Data;
|
epoch_buffer <= epoch_tmrcmp(25 downto 2);
|
|
end if;
|
|
|
|
|
buffer_update <= '0';
|
|
timer_clear <= '0';
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Addr_q )is
|
when "00" =>
|
when "000" =>
|
epoch_setpt(9 downto 2) <= Wr_Data_q;
|
setpt_buffer_b0 <= Wr_Data_q;
|
when "01" =>
|
buffer_pending <= '1';
|
epoch_setpt(17 downto 10) <= Wr_Data_q;
|
|
when "10" =>
|
when "001" =>
|
epoch_setpt(25 downto 18) <= Wr_Data_q;
|
setpt_buffer_b1 <= Wr_Data_q;
|
when "11" =>
|
buffer_pending <= '1';
|
if( Wr_Data_q(0) = '1' )then
|
|
|
when "010" =>
|
|
setpt_buffer_b2 <= Wr_Data_q;
|
|
buffer_pending <= '1';
|
|
|
|
when "011" =>
|
|
buffer_update <= '1';
|
|
buffer_pending <= '0';
|
|
|
|
when "100" | "101" | "110" =>
|
epoch_buffer <= epoch_tmrcmp;
|
epoch_buffer <= epoch_tmrcmp;
|
end if;
|
|
if( Wr_Data_q(1) = '1' )then
|
when "111" =>
|
epoch_tmr <= (others => '0');
|
timer_clear <= '1';
|
end if;
|
when others => null;
|
if( Wr_Data_q(7) = '1' )then
|
end case;
|
epoch_alarm <= '0';
|
|
end if;
|
end if;
|
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
|
Rd_En <= Addr_Match and Rd_Enable;
|
|
if( Rd_En = '1' )then
|
|
case( Reg_Addr_q )is
|
|
when "000" =>
|
|
Rd_Data <= epoch_setpt_b0;
|
|
when "001" =>
|
|
Rd_Data <= epoch_setpt_b1;
|
|
when "010" =>
|
|
Rd_Data <= epoch_setpt_b2;
|
|
when "011" =>
|
|
Rd_Data <= epoch_alarm & buffer_pending & "000000";
|
|
when "100" =>
|
|
Rd_Data <= epoch_buffer_b0(7 downto 0);
|
|
when "101" =>
|
|
Rd_Data <= epoch_buffer_b1(15 downto 8);
|
|
when "110" =>
|
|
Rd_Data <= epoch_buffer_b2(23 downto 16);
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
timer_proc: process( Clock, Reset )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
epoch_setpt <= (others => '0');
|
|
epoch_tmr <= (others => '0');
|
|
epoch_alarm <= '0';
|
|
epoch_alarm_q <= '0';
|
|
Interrupt <= '0';
|
|
|
|
elsif( rising_edge(Clock) )then
|
|
|
|
epoch_tmr <= epoch_tmr + uSec_Tick;
|
|
|
-- Set and hold on alarm condition
|
-- Set and hold on alarm condition
|
if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
|
if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
|
epoch_alarm <= '1';
|
epoch_alarm <= '1';
|
end if;
|
end if;
|
|
|
|
if( buffer_update = '1' )then
|
|
epoch_setpt_u <= setpt_buffer;
|
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
|
-- reduced to 1uS (reproducing the original behavior). Software should
|
|
-- always subtract 4uS (-1) from the desired time to compensate
|
|
epoch_setpt_l <= (others => or_reduce(setpt_buffer));
|
|
epoch_alarm <= '0';
|
|
end if;
|
|
|
|
if( timer_clear = '1' )then
|
|
epoch_setpt <= (others => '0');
|
|
epoch_tmr <= (others => '0');
|
|
epoch_alarm <= '0';
|
|
end if;
|
|
|
epoch_alarm_q <= epoch_alarm;
|
epoch_alarm_q <= epoch_alarm;
|
-- Fire on rising edge of epoch_alarm
|
-- Fire on rising edge of epoch_alarm
|
Interrupt <= epoch_alarm and not epoch_alarm_q;
|
Interrupt <= epoch_alarm and not epoch_alarm_q;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
|
Rd_En <= Addr_Match and Rd_Enable;
|
|
if( Rd_En = '1' )then
|
|
case( Reg_Addr_q )is
|
|
when "00" =>
|
|
Rd_Data <= epoch_buffer(7 downto 0);
|
|
when "01" =>
|
|
Rd_Data <= epoch_buffer(15 downto 8);
|
|
when "10" =>
|
|
Rd_Data <= epoch_buffer(23 downto 16);
|
|
when "11" =>
|
|
Rd_Data <= epoch_alarm & "0000000";
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
