| Line 84... |
Line 84... |
|
|
architecture behave of o8_epoch_timer is
|
architecture behave of o8_epoch_timer is
|
|
|
constant User_Addr : std_logic_vector(15 downto 3)
|
constant User_Addr : std_logic_vector(15 downto 3)
|
:= Address(15 downto 3);
|
:= Address(15 downto 3);
|
|
|
alias Comp_Addr is Bus_Address(15 downto 3);
|
alias Comp_Addr is Bus_Address(15 downto 3);
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
|
|
alias Reg_Addr is Bus_Address(2 downto 0);
|
alias Reg_Addr is Bus_Address(2 downto 0);
|
signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
|
signal Reg_Addr_q : std_logic_vector(2 downto 0) :=
|
|
(others => '0');
|
|
|
signal Wr_En : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
|
|
signal setpt_buffer : std_logic_vector(23 downto 0) := (others => '0');
|
signal setpt_buffer : std_logic_vector(23 downto 0) :=
|
|
(others => '0');
|
|
|
alias setpt_buffer_b0 is setpt_buffer(7 downto 0);
|
alias setpt_buffer_b0 is setpt_buffer(7 downto 0);
|
alias setpt_buffer_b1 is setpt_buffer(15 downto 8);
|
alias setpt_buffer_b1 is setpt_buffer(15 downto 8);
|
alias setpt_buffer_b2 is setpt_buffer(23 downto 16);
|
alias setpt_buffer_b2 is setpt_buffer(23 downto 16);
|
|
|
signal epoch_buffer : std_logic_vector(23 downto 0) := (others => '0');
|
signal buffer_pending : std_logic := '0';
|
|
signal buffer_update : std_logic := '0';
|
|
|
|
signal epoch_buffer : std_logic_vector(23 downto 0) :=
|
|
(others => '0');
|
alias epoch_buffer_b0 is epoch_buffer(7 downto 0);
|
alias epoch_buffer_b0 is epoch_buffer(7 downto 0);
|
alias epoch_buffer_b1 is epoch_buffer(15 downto 8);
|
alias epoch_buffer_b1 is epoch_buffer(15 downto 8);
|
alias epoch_buffer_b2 is epoch_buffer(23 downto 16);
|
alias epoch_buffer_b2 is epoch_buffer(23 downto 16);
|
signal buffer_pending : std_logic := '0';
|
|
signal buffer_update : std_logic := '0';
|
signal capture_epoch : std_logic;
|
signal timer_clear : std_logic := '0';
|
signal timer_clear : std_logic := '0';
|
|
|
signal epoch_tmr : std_logic_vector(25 downto 0) := (others => '0');
|
signal epoch_tmr : std_logic_vector(25 downto 0) :=
|
|
(others => '0');
|
|
|
alias epoch_tmrcmp is epoch_tmr(25 downto 2);
|
alias epoch_tmrcmp is epoch_tmr(25 downto 2);
|
signal epoch_setpt : std_logic_vector(25 downto 0) := (others => '0');
|
|
|
signal epoch_setpt : std_logic_vector(25 downto 0) :=
|
|
(others => '0');
|
|
|
alias epoch_setpt_b0 is epoch_setpt(7 downto 0);
|
alias epoch_setpt_b0 is epoch_setpt(7 downto 0);
|
alias epoch_setpt_b1 is epoch_setpt(15 downto 8);
|
alias epoch_setpt_b1 is epoch_setpt(15 downto 8);
|
alias epoch_setpt_b2 is epoch_setpt(23 downto 16);
|
alias epoch_setpt_b2 is epoch_setpt(23 downto 16);
|
alias epoch_setpt_u is epoch_setpt(25 downto 2);
|
alias epoch_setpt_u is epoch_setpt(25 downto 2);
|
alias epoch_setpt_l is epoch_setpt(1 downto 0);
|
alias epoch_setpt_l is epoch_setpt(1 downto 0);
|
|
|
signal epoch_alarm : std_logic := '0';
|
signal epoch_alarm : std_logic := '0';
|
signal epoch_alarm_q : std_logic := '0';
|
signal epoch_alarm_q : std_logic := '0';
|
|
|
begin
|
begin
|
|
|
| Line 131... |
Line 145... |
Reg_Addr_q <= (others => '0');
|
Reg_Addr_q <= (others => '0');
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
setpt_buffer <= (others => '0');
|
setpt_buffer <= (others => '0');
|
epoch_buffer <= (others => '0');
|
|
buffer_pending <= '0';
|
buffer_pending <= '0';
|
buffer_update <= '0';
|
buffer_update <= '0';
|
|
capture_epoch <= '0';
|
timer_clear <= '0';
|
timer_clear <= '0';
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
|
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Addr_q <= Reg_Addr;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
|
|
buffer_update <= '0';
|
buffer_update <= '0';
|
|
capture_epoch <= '0';
|
timer_clear <= '0';
|
timer_clear <= '0';
|
|
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Addr_q )is
|
when "000" =>
|
when "000" =>
|
setpt_buffer_b0 <= Wr_Data_q;
|
setpt_buffer_b0 <= Wr_Data_q;
|
buffer_pending <= '1';
|
buffer_pending <= '1';
|
| Line 162... |
Line 178... |
when "011" =>
|
when "011" =>
|
buffer_update <= '1';
|
buffer_update <= '1';
|
buffer_pending <= '0';
|
buffer_pending <= '0';
|
|
|
when "100" | "101" | "110" =>
|
when "100" | "101" | "110" =>
|
epoch_buffer <= epoch_tmrcmp;
|
capture_epoch <= '1';
|
|
|
when "111" =>
|
when "111" =>
|
timer_clear <= '1';
|
timer_clear <= '1';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
| Line 198... |
Line 214... |
|
|
timer_proc: process( Clock, Reset )
|
timer_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
epoch_setpt <= (others => '0');
|
epoch_setpt <= (others => '0');
|
|
epoch_buffer <= (others => '0');
|
epoch_tmr <= (others => '0');
|
epoch_tmr <= (others => '0');
|
epoch_alarm <= '0';
|
epoch_alarm <= '0';
|
epoch_alarm_q <= '0';
|
epoch_alarm_q <= '0';
|
Interrupt <= '0';
|
Interrupt <= '0';
|
|
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
|
epoch_tmr <= epoch_tmr + uSec_Tick;
|
epoch_tmr <= epoch_tmr + uSec_Tick;
|
|
|
-- Set and hold on alarm condition
|
if( epoch_tmr > epoch_setpt )then
|
if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
|
epoch_alarm <= or_reduce(epoch_setpt);
|
epoch_alarm <= '1';
|
|
end if;
|
end if;
|
|
|
if( buffer_update = '1' )then
|
if( buffer_update = '1' )then
|
epoch_setpt_u <= setpt_buffer;
|
epoch_setpt_u <= setpt_buffer;
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
-- reduced to 1uS (reproducing the original behavior). Software should
|
-- reduced to 1uS (reproducing the original behavior). Software
|
-- always subtract 4uS (-1) from the desired time to compensate
|
-- should always subtract 4uS (-1) from the desired time to compensate
|
epoch_setpt_l <= (others => or_reduce(setpt_buffer));
|
epoch_setpt_l <= (others => or_reduce(setpt_buffer));
|
epoch_alarm <= '0';
|
epoch_alarm <= '0';
|
end if;
|
end if;
|
|
|
if( timer_clear = '1' )then
|
if( timer_clear = '1' )then
|
| Line 228... |
Line 244... |
epoch_tmr <= (others => '0');
|
epoch_tmr <= (others => '0');
|
epoch_alarm <= '0';
|
epoch_alarm <= '0';
|
end if;
|
end if;
|
|
|
epoch_alarm_q <= epoch_alarm;
|
epoch_alarm_q <= epoch_alarm;
|
-- Fire on rising edge of epoch_alarm
|
|
Interrupt <= epoch_alarm and not epoch_alarm_q;
|
Interrupt <= epoch_alarm and not epoch_alarm_q;
|
|
|
|
if( capture_epoch = '1' )then
|
|
epoch_buffer <= epoch_tmrcmp;
|
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
