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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Diff between revs 222 and 223

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Rev 222	Rev 223
Line 71...	Line 71...
`port(`	`port(`
`Clock : in std_logic;`	`Clock : in std_logic;`
`Reset : in std_logic;`	`Reset : in std_logic;`
`uSec_Tick : in std_logic;`	`uSec_Tick : in std_logic;`
`--`	`--`
`Bus_Address : in ADDRESS_TYPE;`	`Open8_Bus : in OPEN8_BUS_TYPE;`
`Wr_Enable : in std_logic;`
`Wr_Data : in DATA_TYPE;`
`Rd_Enable : in std_logic;`
`Rd_Data : out DATA_TYPE;`	`Rd_Data : out DATA_TYPE;`
`Interrupt : out std_logic`	`Interrupt : out std_logic`
`);`	`);`
`end entity;`	`end entity;`

`architecture behave of o8_epoch_timer is`	`architecture behave of o8_epoch_timer is`

`constant User_Addr : std_logic_vector(15 downto 3)`	`constant User_Addr : std_logic_vector(15 downto 3)`
`:= Address(15 downto 3);`	`:= Address(15 downto 3);`

`alias Comp_Addr is Bus_Address(15 downto 3);`	`alias Comp_Addr is Open8_Bus.Address(15 downto 3);`
`signal Addr_Match : std_logic := '0';`	`signal Addr_Match : std_logic := '0';`

`alias Reg_Addr is Bus_Address(2 downto 0);`	`alias Reg_Addr is Open8_Bus.Address(2 downto 0);`
`signal Reg_Addr_q : std_logic_vector(2 downto 0) :=`	`signal Reg_Addr_q : std_logic_vector(2 downto 0) :=`
`(others => '0');`	`(others => '0');`

`signal Wr_En : std_logic := '0';`	`signal Wr_En : std_logic := '0';`
`signal Wr_Data_q : DATA_TYPE := x"00";`	`signal Wr_Data_q : DATA_TYPE := x"00";`
Line 152...	Line 149...
`capture_epoch <= '0';`	`capture_epoch <= '0';`
`timer_clear <= '0';`	`timer_clear <= '0';`
`elsif( rising_edge( Clock ) )then`	`elsif( rising_edge( Clock ) )then`

`Reg_Addr_q <= Reg_Addr;`	`Reg_Addr_q <= Reg_Addr;`
`Wr_En <= Addr_Match and Wr_Enable;`	`Wr_En <= Addr_Match and Open8_Bus.Wr_En;`
`Wr_Data_q <= Wr_Data;`	`Wr_Data_q <= Open8_Bus.Wr_Data;`

`buffer_update <= '0';`	`buffer_update <= '0';`
`capture_epoch <= '0';`	`capture_epoch <= '0';`
`timer_clear <= '0';`	`timer_clear <= '0';`

Line 187...	Line 184...
`when others => null;`	`when others => null;`
`end case;`	`end case;`
`end if;`	`end if;`

`Rd_Data <= OPEN8_NULLBUS;`	`Rd_Data <= OPEN8_NULLBUS;`
`Rd_En <= Addr_Match and Rd_Enable;`	`Rd_En <= Addr_Match and Open8_Bus.Rd_En;`
`if( Rd_En = '1' )then`	`if( Rd_En = '1' )then`
`case( Reg_Addr_q )is`	`case( Reg_Addr_q )is`
`when "000" =>`	`when "000" =>`
`Rd_Data <= epoch_setpt_b0;`	`Rd_Data <= epoch_setpt_b0;`
`when "001" =>`	`when "001" =>`

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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Diff between revs 222 and 223