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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 52... Line 52...
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
-- Seth Henry      12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
-- Seth Henry      04/10/20 Overhauled the register interface of the timer to
-- Seth Henry      04/10/20 Overhauled the register interface of the timer to
--                           make the interface more sensible to software.
--                           make the interface more sensible to software.
-- Seth Henry      04/160/20 Modified to make use of Open8 bus record
-- Seth Henry      04/160/20 Modified to make use of Open8 bus record
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 68... Line 69...
generic(
generic(
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic
  Interrupt                  : out std_logic
);
);
end entity;
end entity;
 
 
Line 85... Line 87...
                               := Address(15 downto 3);
                               := Address(15 downto 3);
 
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
 
 
  alias  Reg_Addr            is Open8_Bus.Address(2 downto 0);
  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
  signal Reg_Addr_q          : std_logic_vector(2 downto 0) :=
  signal Reg_Sel_q           : std_logic_vector(2 downto 0) := "000";
                                (others => '0');
  signal Wr_En_d             : std_logic := '0';
 
  signal Wr_En_q             : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Rd_En               : std_logic := '0';
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal setpt_buffer        : std_logic_vector(23 downto 0) :=
  signal setpt_buffer        : std_logic_vector(23 downto 0) :=
                                (others => '0');
                                (others => '0');
 
 
  alias  setpt_buffer_b0     is setpt_buffer(7 downto 0);
  alias  setpt_buffer_b0     is setpt_buffer(7 downto 0);
Line 132... Line 135...
  signal epoch_alarm_q       : std_logic := '0';
  signal epoch_alarm_q       : std_logic := '0';
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Wr_Data_q              <= (others => '0');
      Reg_Sel_q              <= "000";
      Reg_Addr_q             <= (others => '0');
      Wr_En_q                <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      setpt_buffer           <= (others => '0');
      setpt_buffer           <= (others => '0');
      buffer_pending         <= '0';
      buffer_pending         <= '0';
      buffer_update          <= '0';
      buffer_update          <= '0';
      capture_epoch          <= '0';
      capture_epoch          <= '0';
      timer_clear            <= '0';
      timer_clear            <= '0';
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
 
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Reg_Addr_q             <= Reg_Addr;
      Wr_En_q                <= Wr_En_d;
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_Data_q              <= Wr_Data_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
 
 
 
      buffer_update          <= '0';
      buffer_update          <= '0';
      capture_epoch          <= '0';
      capture_epoch          <= '0';
      timer_clear            <= '0';
      timer_clear            <= '0';
 
 
      if( Wr_En = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Addr_q )is
        case( Reg_Sel_q )is
          when "000" =>
          when "000" =>
            setpt_buffer_b0  <= Wr_Data_q;
            setpt_buffer_b0  <= Wr_Data_q;
            buffer_pending   <= '1';
            buffer_pending   <= '1';
 
 
          when "001" =>
          when "001" =>
Line 183... Line 189...
            timer_clear      <= '1';
            timer_clear      <= '1';
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      if( Rd_En_q = '1' )then
      if( Rd_En = '1' )then
        case( Reg_Sel_q )is
        case( Reg_Addr_q )is
 
          when "000" =>
          when "000" =>
            Rd_Data          <= epoch_setpt_b0;
            Rd_Data          <= epoch_setpt_b0;
          when "001" =>
          when "001" =>
            Rd_Data          <= epoch_setpt_b1;
            Rd_Data          <= epoch_setpt_b1;
          when "010" =>
          when "010" =>

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