| Line 52... |
Line 52... |
-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
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-- Seth Henry 12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
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-- Seth Henry 04/10/20 Overhauled the register interface of the timer to
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-- Seth Henry 04/10/20 Overhauled the register interface of the timer to
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-- make the interface more sensible to software.
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-- make the interface more sensible to software.
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-- Seth Henry 04/160/20 Modified to make use of Open8 bus record
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-- Seth Henry 04/160/20 Modified to make use of Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 68... |
Line 69... |
generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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| Line 85... |
Line 87... |
:= Address(15 downto 3);
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:= Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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|
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0) :=
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
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(others => '0');
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal setpt_buffer : std_logic_vector(23 downto 0) :=
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signal setpt_buffer : std_logic_vector(23 downto 0) :=
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(others => '0');
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(others => '0');
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alias setpt_buffer_b0 is setpt_buffer(7 downto 0);
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alias setpt_buffer_b0 is setpt_buffer(7 downto 0);
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| Line 132... |
Line 135... |
signal epoch_alarm_q : std_logic := '0';
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signal epoch_alarm_q : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_Data_q <= (others => '0');
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Reg_Sel_q <= "000";
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Reg_Addr_q <= (others => '0');
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Wr_En_q <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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setpt_buffer <= (others => '0');
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setpt_buffer <= (others => '0');
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buffer_pending <= '0';
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buffer_pending <= '0';
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buffer_update <= '0';
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buffer_update <= '0';
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capture_epoch <= '0';
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capture_epoch <= '0';
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timer_clear <= '0';
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timer_clear <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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|
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Reg_Addr_q <= Reg_Addr;
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Wr_En_q <= Wr_En_d;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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buffer_update <= '0';
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buffer_update <= '0';
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capture_epoch <= '0';
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capture_epoch <= '0';
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timer_clear <= '0';
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timer_clear <= '0';
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Sel_q )is
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when "000" =>
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when "000" =>
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setpt_buffer_b0 <= Wr_Data_q;
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setpt_buffer_b0 <= Wr_Data_q;
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buffer_pending <= '1';
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buffer_pending <= '1';
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when "001" =>
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when "001" =>
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| Line 183... |
Line 189... |
timer_clear <= '1';
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timer_clear <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= epoch_setpt_b0;
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Rd_Data <= epoch_setpt_b0;
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when "001" =>
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when "001" =>
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Rd_Data <= epoch_setpt_b1;
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Rd_Data <= epoch_setpt_b1;
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when "010" =>
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when "010" =>
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