| Line 36... |
Line 36... |
-- 0x3 AAAAAAAA B3 of Buffered Setpoint (W) or Current Setpoint(R)
|
-- 0x3 AAAAAAAA B3 of Buffered Setpoint (W) or Current Setpoint(R)
|
-- 0x4 AAAAAAAA B0 of Current Epoch Time(RO)
|
-- 0x4 AAAAAAAA B0 of Current Epoch Time(RO)
|
-- 0x5 AAAAAAAA B1 of Current Epoch Time(RO)
|
-- 0x5 AAAAAAAA B1 of Current Epoch Time(RO)
|
-- 0x6 AAAAAAAA B2 of Current Epoch Time(RO)
|
-- 0x6 AAAAAAAA B2 of Current Epoch Time(RO)
|
-- 0x7 AAAAAAAA B3 of Current Epoch Time(RO)
|
-- 0x7 AAAAAAAA B3 of Current Epoch Time(RO)
|
|
-- Note that any write to 0x04,0x05, 0x06, or 0x07 will copy
|
|
-- the current epoch time to a readable output buffer
|
-- 0x8 xxxxxxxx (not used - returns 0x00)
|
-- 0x8 xxxxxxxx (not used - returns 0x00)
|
-- 0x9 xxxxxxxx (not used - returns 0x00)
|
-- 0x9 xxxxxxxx (not used - returns 0x00)
|
-- 0xA xxxxxxxx (not used - returns 0x00)
|
-- 0xA xxxxxxxx (not used - returns 0x00)
|
-- 0xB xxxxxxxx (not used - returns 0x00)
|
-- 0xB xxxxxxxx (not used - returns 0x00)
|
-- 0xC xxxxxxxx (not used - returns 0x00)
|
-- 0xC xxxxxxxx (not used - returns 0x00)
|
| Line 49... |
Line 51... |
-- 0xF BA------ Status of buffer/alarm (1 = pending, 0 = current)
|
-- 0xF BA------ Status of buffer/alarm (1 = pending, 0 = current)
|
-- A = Pending status (R)
|
-- A = Pending status (R)
|
-- B = Alarm status (R)
|
-- B = Alarm status (R)
|
-- Note that any write will update the internal set point
|
-- Note that any write will update the internal set point
|
-- and clear the alarm
|
-- and clear the alarm
|
-- Note that any write to 0x04,0x05, or 0x06 will copy the
|
|
-- current epoch time to a readable output buffer
|
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
|
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
|
-- change.
|
-- change.
|
-- Seth Henry 04/16/20 Modifiefd to make use of Open8 bus record
|
-- Seth Henry 04/16/20 Modifiefd to make use of Open8 bus record
|
|
-- Seth Henry 05/18/20 Added write qualification input
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 74... |
Line 75... |
generic(
|
generic(
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
|
Write_Qual : in std_logic := '1';
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Interrupt : out std_logic
|
Interrupt : out std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
| Line 91... |
Line 93... |
:= Address(15 downto 4);
|
:= Address(15 downto 4);
|
|
|
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
|
|
alias Reg_Addr is Open8_Bus.Address(3 downto 0);
|
alias Reg_Sel_d is Open8_Bus.Address(3 downto 0);
|
signal Reg_Addr_q : std_logic_vector(3 downto 0) :=
|
signal Reg_Sel_q : std_logic_vector(3 downto 0) := "0000";
|
(others => '0');
|
signal Wr_En_d : std_logic := '0';
|
|
signal Wr_En_q : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic := '0';
|
signal Rd_En_d : std_logic := '0';
|
|
signal Rd_En_q : std_logic := '0';
|
|
|
signal setpt_buffer : std_logic_vector(31 downto 0) :=
|
signal setpt_buffer : std_logic_vector(31 downto 0) :=
|
(others => '0');
|
(others => '0');
|
|
|
alias setpt_buffer_b0 is setpt_buffer( 7 downto 0);
|
alias setpt_buffer_b0 is setpt_buffer( 7 downto 0);
|
| Line 140... |
Line 143... |
signal epoch_alarm_q : std_logic := '0';
|
signal epoch_alarm_q : std_logic := '0';
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
|
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Wr_Data_q <= (others => '0');
|
Reg_Sel_q <= "0000";
|
Reg_Addr_q <= (others => '0');
|
Wr_En_q <= '0';
|
Wr_En <= '0';
|
Wr_Data_q <= x"00";
|
Rd_En <= '0';
|
Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
setpt_buffer <= (others => '0');
|
setpt_buffer <= (others => '0');
|
buffer_pending <= '0';
|
buffer_pending <= '0';
|
buffer_update <= '0';
|
buffer_update <= '0';
|
capture_epoch <= '0';
|
capture_epoch <= '0';
|
timer_clear <= '0';
|
timer_clear <= '0';
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
|
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Sel_q <= Reg_Sel_d;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
Wr_En_q <= Wr_En_d;
|
|
Wr_Data_q <= Wr_Data_d;
|
|
|
buffer_update <= '0';
|
buffer_update <= '0';
|
timer_clear <= '0';
|
timer_clear <= '0';
|
capture_epoch <= '0';
|
capture_epoch <= '0';
|
|
|
if( Wr_En = '1' )then
|
if( Wr_En_q = '1' and Write_Qual = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Sel_q )is
|
when x"0" =>
|
when x"0" =>
|
setpt_buffer_b0 <= Wr_Data_q;
|
setpt_buffer_b0 <= Wr_Data_q;
|
buffer_pending <= '1';
|
buffer_pending <= '1';
|
|
|
when x"1" =>
|
when x"1" =>
|
| Line 197... |
Line 204... |
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_q <= Rd_En_d;
|
if( Rd_En = '1' )then
|
if( Rd_En_q = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Sel_q )is
|
when x"0" =>
|
when x"0" =>
|
Rd_Data <= epoch_setpt_b0;
|
Rd_Data <= epoch_setpt_b0;
|
when x"1" =>
|
when x"1" =>
|
Rd_Data <= epoch_setpt_b1;
|
Rd_Data <= epoch_setpt_b1;
|
when x"2" =>
|
when x"2" =>
|
