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-- Copyright (c)2013 Jeremy Seth Henry
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-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_gpin
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-- VHDL Units : o8_gpin
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-- Description: Provides a single 8-bit input register
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-- Description: Provides a single 8-bit input register
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--
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-- Note: Cut the path between GPIN and GPIN_q1 for timing analysis
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_gpin" to fit "theme"
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-- Seth Henry 12/20/19 Added metastability registers
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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signal GPIN_q1 : DATA_TYPE;
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signal GPIN_q2 : DATA_TYPE;
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signal User_In : DATA_TYPE;
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signal User_In : DATA_TYPE;
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begin
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begin
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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GPIN_q1 <= x"00";
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GPIN_q2 <= x"00";
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User_In <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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User_In <= GPIN; -- first stage of double buffer
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GPIN_q1 <= GPIN;
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GPIN_q2 <= GPIN_q1;
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User_In <= GPIN_q2;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match;
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Rd_En <= Addr_Match;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= User_In;
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Rd_Data <= User_In;
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