URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpin.vhd] - Diff between revs 189 and 191
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 189 |
Rev 191 |
| Line 73... |
Line 73... |
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= x"00";
|
Rd_Data <= OPEN8_NULLBUS;
|
GPIN_q1 <= x"00";
|
GPIN_q1 <= x"00";
|
GPIN_q2 <= x"00";
|
GPIN_q2 <= x"00";
|
User_In <= x"00";
|
User_In <= x"00";
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
GPIN_q1 <= GPIN;
|
GPIN_q1 <= GPIN;
|
GPIN_q2 <= GPIN_q1;
|
GPIN_q2 <= GPIN_q1;
|
User_In <= GPIN_q2;
|
User_In <= GPIN_q2;
|
|
|
Rd_Data <= (others => '0');
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match;
|
Rd_En <= Addr_Match;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= User_In;
|
Rd_Data <= User_In;
|
end if;
|
end if;
|
end if;
|
end if;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
