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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpin.vhd] - Diff between revs 213 and 223

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Rev 213 Rev 223
Line 47... Line 47...
);
);
port(
port(
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
  --
  --
  Bus_Address                : in  ADDRESS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Enable                  : in  std_logic;
 
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  GPIN                       : in  DATA_TYPE
  GPIN                       : in  DATA_TYPE
);
);
end entity;
end entity;
 
 
architecture behave of o8_gpin is
architecture behave of o8_gpin is
 
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  alias  Comp_Addr           is Bus_Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic;
  signal Addr_Match          : std_logic;
  signal Rd_En               : std_logic;
  signal Rd_En               : std_logic;
 
 
  signal GPIN_q1             : DATA_TYPE;
  signal GPIN_q1             : DATA_TYPE;
  signal GPIN_q2             : DATA_TYPE;
  signal GPIN_q2             : DATA_TYPE;
  signal User_In             : DATA_TYPE;
  signal User_In             : DATA_TYPE;
 
 
begin
begin
 
 
  Addr_Match                 <= Rd_Enable when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
 
                                '0';
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Rd_En                  <= '0';
      Rd_En                  <= '0';

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