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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpin.vhd] - Diff between revs 223 and 224
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Rev 224 |
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_gpin" to fit "theme"
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-- Seth Henry 12/19/19 Renamed to "o8_gpin" to fit "theme"
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-- Seth Henry 12/20/19 Added metastability registers
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-- Seth Henry 12/20/19 Added metastability registers
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-- Seth Henry 04/10/20 Code Cleanup
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-- Seth Henry 04/10/20 Code Cleanup
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_gpin is
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entity o8_gpin is
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generic(
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generic(
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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GPIN : in DATA_TYPE
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GPIN : in DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_gpin is
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architecture behave of o8_gpin is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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