| Line 21... |
Line 21... |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- VHDL Units : o8_gpio
|
-- VHDL Units : o8_gpio
|
-- Description: Provides a single 8-bit GPIO register
|
-- Description: Provides a single 8-bit GPIO register
|
|
--
|
|
-- Register Map:
|
|
-- Offset Bitfield Description Read/Write
|
|
-- 0x00 AAAAAAAA Output Register (RW)
|
|
-- 0x01 AAAAAAAA Direction Register (RW)
|
|
-- 0x03 AAAAAAAA Input Register (RO)
|
|
--
|
|
-- Revision History
|
|
-- Author Date Change
|
|
------------------ -------- ---------------------------------------------------
|
|
-- Seth Henry 12/20/13 Design Start
|
|
-- Seth Henry 04/10/20 Code cleanup and register documentation
|
|
-- Also removed "input only" generic, as there is a
|
|
-- separate module for that
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
library work;
|
library work;
|
| Line 33... |
Line 47... |
entity o8_gpio is
|
entity o8_gpio is
|
generic(
|
generic(
|
Default_Out : DATA_TYPE := x"00";
|
Default_Out : DATA_TYPE := x"00";
|
Default_En : DATA_TYPE := x"00";
|
Default_En : DATA_TYPE := x"00";
|
Reset_Level : std_logic := '1';
|
Reset_Level : std_logic := '1';
|
Input_Only : boolean := false;
|
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
| Line 76... |
Line 89... |
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Sel <= "00";
|
Reg_Sel <= "00";
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( not Input_Only )then
|
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
User_Out <= Default_Out;
|
User_Out <= Default_Out;
|
User_En <= Default_En;
|
User_En <= Default_En;
|
end if;
|
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Sel <= Reg_Addr;
|
Reg_Sel <= Reg_Addr;
|
|
|
if( not Input_Only )then
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Sel )is
|
case( Reg_Sel )is
|
when "00" =>
|
when "00" =>
|
| Line 97... |
Line 107... |
when "01" =>
|
when "01" =>
|
User_En <= Wr_Data_q;
|
User_En <= Wr_Data_q;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
|
|
|
User_In <= GPIO;
|
User_In <= GPIO;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Rd_Enable;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
if( Input_Only )then
|
|
Rd_Data <= User_In;
|
Rd_Data <= User_In;
|
else
|
|
case( Reg_Sel )is
|
case( Reg_Sel )is
|
when "00" =>
|
when "00" =>
|
Rd_Data <= User_Out;
|
Rd_Data <= User_Out;
|
when "01" =>
|
when "01" =>
|
Rd_Data <= User_En;
|
Rd_Data <= User_En;
|
| Line 118... |
Line 125... |
Rd_Data <= User_In;
|
Rd_Data <= User_In;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
end process;
|
|
|
Input_Only_is_True: if( Input_Only )generate
|
|
GPIO <= (others => 'Z');
|
|
end generate;
|
|
|
|
Input_Only_is_False: if( not Input_Only )generate
|
|
|
|
Output_Ctl_proc: process( User_Out, User_En )
|
Output_Ctl_proc: process( User_Out, User_En )
|
begin
|
begin
|
for i in 0 to 7 loop
|
for i in 0 to 7 loop
|
GPIO(i) <= 'Z';
|
GPIO(i) <= 'Z';
|
if( User_En(i) = '1' )then
|
if( User_En(i) = '1' )then
|
GPIO(i) <= User_Out(i);
|
GPIO(i) <= User_Out(i);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end process;
|
end process;
|
|
|
end generate;
|
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
