URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpout.vhd] - Diff between revs 172 and 191
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 172 |
Rev 191 |
| Line 79... |
Line 79... |
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Sel <= '0';
|
Reg_Sel <= '0';
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= x"00";
|
Rd_Data <= OPEN8_NULLBUS;
|
User_Out <= Default_Out;
|
User_Out <= Default_Out;
|
if( not Disable_Tristate)then
|
if( not Disable_Tristate)then
|
User_En <= Default_En;
|
User_En <= Default_En;
|
end if;
|
end if;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
| Line 100... |
Line 100... |
User_En <= Wr_Data_q;
|
User_En <= Wr_Data_q;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
Rd_Data <= (others => '0');
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Rd_Enable;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= User_Out;
|
Rd_Data <= User_Out;
|
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
|
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
|
Rd_Data <= User_En;
|
Rd_Data <= User_En;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.