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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpout.vhd] - Diff between revs 172 and 191
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| Rev 172 |
Rev 191 |
| Line 79... |
Line 79... |
if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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User_Out <= Default_Out;
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User_Out <= Default_Out;
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if( not Disable_Tristate)then
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if( not Disable_Tristate)then
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User_En <= Default_En;
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User_En <= Default_En;
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end if;
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end if;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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| Line 100... |
Line 100... |
User_En <= Wr_Data_q;
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User_En <= Wr_Data_q;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= User_Out;
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Rd_Data <= User_Out;
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if( (Reg_Sel = '1') and (not Disable_Tristate) )then
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if( (Reg_Sel = '1') and (not Disable_Tristate) )then
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Rd_Data <= User_En;
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Rd_Data <= User_En;
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