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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- Copyright (c)2011, 20219, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_gpout
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-- VHDL Units : o8_gpout
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-- Description: Provides a single 8-bit GP output register with selectable
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-- Description: Provides a single 8-bit GP output register with selectable
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-- : tri-state control.
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-- : tri-state control.
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-- Notes : Requires 1 bit from the address bus (two locations).
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--
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-- : Sequential instantiations should be separated by 2.
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Output Register (RW)
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-- 0x01 AAAAAAAA Enable/Tri-State Register (RW)
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--
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-- Note that setting a bit to '1' will enable the pin for output, while
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-- setting it to a '0' will tri-state the pin.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
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-- Seth Henry 04/10/20 Code Cleanup and comments
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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