| Line 56... |
Line 56... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
GPO : out DATA_TYPE
|
GPO : out DATA_TYPE
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_gpout is
|
architecture behave of o8_gpout is
|
|
|
constant User_Addr : std_logic_vector(15 downto 1)
|
constant User_Addr : std_logic_vector(15 downto 1)
|
:= Address(15 downto 1);
|
:= Address(15 downto 1);
|
alias Comp_Addr is Bus_Address(15 downto 1);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
|
alias Reg_Addr is Bus_Address(0);
|
alias Reg_Addr is Open8_Bus.Address(0);
|
signal Reg_Sel : std_logic;
|
signal Reg_Sel : std_logic := '0';
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic := '0';
|
signal Wr_En : std_logic;
|
signal Wr_En : std_logic := '0';
|
signal Wr_Data_q : DATA_TYPE;
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic;
|
signal Rd_En : std_logic := '0';
|
|
|
signal User_Out : DATA_TYPE;
|
signal User_Out : DATA_TYPE := x"00";
|
signal User_En : DATA_TYPE;
|
signal User_En : DATA_TYPE := x"00";
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
|
| Line 99... |
Line 96... |
if( not Disable_Tristate)then
|
if( not Disable_Tristate)then
|
User_En <= Default_En;
|
User_En <= Default_En;
|
end if;
|
end if;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Sel <= Reg_Addr;
|
Reg_Sel <= Reg_Addr;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
if( Disable_Tristate )then
|
if( Disable_Tristate )then
|
User_Out <= Wr_Data_q;
|
User_Out <= Wr_Data_q;
|
else
|
else
|
if( Reg_Sel = '0' )then
|
if( Reg_Sel = '0' )then
|
| Line 114... |
Line 111... |
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= User_Out;
|
Rd_Data <= User_Out;
|
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
|
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
|
Rd_Data <= User_En;
|
Rd_Data <= User_En;
|
end if;
|
end if;
|
