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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpout.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 37... Line 37...
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      12/19/19 Renamed to "o8_gpout" to fit "theme"
-- Seth Henry      12/19/19 Renamed to "o8_gpout" to fit "theme"
-- Seth Henry      04/10/20 Code Cleanup and comments
-- Seth Henry      04/10/20 Code Cleanup and comments
 
-- Seth Henry      04/16/20 Modified to make use of Open8 bus record
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
library work;
library work;
Line 49... Line 50...
entity o8_gpout is
entity o8_gpout is
generic(
generic(
  Default_Out           : DATA_TYPE := x"00";
  Default_Out           : DATA_TYPE := x"00";
  Default_En            : DATA_TYPE := x"00";
  Default_En            : DATA_TYPE := x"00";
  Disable_Tristate      : boolean   := false;
  Disable_Tristate      : boolean   := false;
  Reset_Level           : std_logic;
 
  Address               : ADDRESS_TYPE
  Address               : ADDRESS_TYPE
);
);
port(
port(
  Clock                 : in  std_logic;
 
  Reset                 : in  std_logic;
 
  --
 
  Open8_Bus             : in  OPEN8_BUS_TYPE;
  Open8_Bus             : in  OPEN8_BUS_TYPE;
  Rd_Data               : out DATA_TYPE;
  Rd_Data               : out DATA_TYPE;
  --
  --
  GPO                   : out DATA_TYPE
  GPO                   : out DATA_TYPE
);
);
end entity;
end entity;
 
 
architecture behave of o8_gpout is
architecture behave of o8_gpout is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
 
  constant User_Addr    : std_logic_vector(15 downto 1)
  constant User_Addr    : std_logic_vector(15 downto 1)
                          := Address(15 downto 1);
                          := Address(15 downto 1);
  alias  Comp_Addr      is Open8_Bus.Address(15 downto 1);
  alias  Comp_Addr      is Open8_Bus.Address(15 downto 1);
  alias  Reg_Addr       is Open8_Bus.Address(0);
  alias  Reg_Addr       is Open8_Bus.Address(0);
  signal Reg_Sel        : std_logic := '0';
  signal Reg_Sel        : std_logic := '0';

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