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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
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-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
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-- Seth Henry 04/10/20 Code Cleanup and comments
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-- Seth Henry 04/10/20 Code Cleanup and comments
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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Line 49... |
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entity o8_gpout is
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entity o8_gpout is
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generic(
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generic(
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Default_Out : DATA_TYPE := x"00";
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Default_Out : DATA_TYPE := x"00";
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Default_En : DATA_TYPE := x"00";
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Default_En : DATA_TYPE := x"00";
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Disable_Tristate : boolean := false;
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Disable_Tristate : boolean := false;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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GPO : out DATA_TYPE
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GPO : out DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_gpout is
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architecture behave of o8_gpout is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 1)
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constant User_Addr : std_logic_vector(15 downto 1)
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:= Address(15 downto 1);
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:= Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Reg_Addr is Open8_Bus.Address(0);
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alias Reg_Addr is Open8_Bus.Address(0);
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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