| Line 38... |
Line 38... |
------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
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-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
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-- Seth Henry 04/10/20 Code Cleanup and comments
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-- Seth Henry 04/10/20 Code Cleanup and comments
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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| Line 54... |
Line 55... |
Disable_Tristate : boolean := false;
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Disable_Tristate : boolean := false;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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GPO : out DATA_TYPE
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GPO : out DATA_TYPE
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);
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);
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end entity;
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end entity;
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| Line 68... |
Line 70... |
alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 1)
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constant User_Addr : std_logic_vector(15 downto 1)
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:= Address(15 downto 1);
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:= Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Reg_Addr is Open8_Bus.Address(0);
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signal Reg_Sel : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal User_Out : DATA_TYPE := x"00";
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signal User_Out : DATA_TYPE := x"00";
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signal User_En : DATA_TYPE := x"00";
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signal User_En : DATA_TYPE := x"00";
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begin
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begin
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| Line 85... |
Line 90... |
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= '0';
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Reg_Sel_q <= '0';
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Wr_En <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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User_Out <= Default_Out;
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User_Out <= Default_Out;
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if( not Disable_Tristate)then
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if( not Disable_Tristate)then
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User_En <= Default_En;
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User_En <= Default_En;
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end if;
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end if;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En_q <= Wr_En_d;
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if( Wr_En = '1' )then
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Wr_Data_q <= Wr_Data_d;
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if( Wr_En_q = '1' )then
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if( Disable_Tristate )then
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if( Disable_Tristate )then
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User_Out <= Wr_Data_q;
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User_Out <= Wr_Data_q;
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else
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else
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if( Reg_Sel = '0' )then
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if( Reg_Sel_q = '0' )then
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User_Out <= Wr_Data_q;
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User_Out <= Wr_Data_q;
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else
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else
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User_En <= Wr_Data_q;
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User_En <= Wr_Data_q;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= User_Out;
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Rd_Data <= User_Out;
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if( (Reg_Sel = '1') and (not Disable_Tristate) )then
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if( (Reg_Sel_q = '1') and (not Disable_Tristate) )then
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Rd_Data <= User_En;
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Rd_Data <= User_En;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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