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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_4b.vhd] - Diff between revs 189 and 191
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| Rev 189 |
Rev 191 |
| Line 258... |
Line 258... |
if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Reg_Data <= x"00";
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Reg_Data <= x"00";
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| Line 288... |
Line 288... |
LCD_Bright <= Wr_Data_q;
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LCD_Bright <= Wr_Data_q;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Rd_Data(7) <= Tx_Ready;
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Rd_Data(7) <= Tx_Ready;
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