| Line 28... |
Line 28... |
-- module, allowing client firmware to use a simple register
|
-- module, allowing client firmware to use a simple register
|
-- interface to program the LCD panel.
|
-- interface to program the LCD panel.
|
-- Init routine initializes the display and displays a single
|
-- Init routine initializes the display and displays a single
|
-- character to demonstrate correct function, then listens for
|
-- character to demonstrate correct function, then listens for
|
-- user data on its external interface.
|
-- user data on its external interface.
|
|
--
|
|
-- Register Map
|
|
-- Address Function
|
|
-- Offset Bitfield Description Read/Write
|
|
-- 0x0 AAAAAAAA LCD Register Write (Write-only)
|
|
-- 0x1 AAAAAAAA LCD Data Write (Write-only)
|
|
-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
|
|
-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
|
|
--
|
|
--------------------------------------------------------------------------------
|
|
-- LCD Controller
|
|
--------------------------------------------------------------------------------
|
|
--
|
|
-- LCD Instruction Set
|
|
-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
|
|
------------------------------------------------------------------------
|
|
-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
|
|
-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
|
|
-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
|
|
-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
|
|
-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
|
|
-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
|
|
-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
|
|
-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
|
|
|
|
-- Notes:
|
|
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
|
|
-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
|
|
-- D = Display On/Off (1 = on, 0 = off)
|
|
-- C = Cursor On/Off (1 = on, 0 = off)
|
|
-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
|
|
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
|
|
-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
|
|
-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
|
|
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
|
|
-- A = Address (see data sheet for usage)
|
|
--
|
|
-- Revision History
|
|
-- Author Date Change
|
|
------------------ -------- ---------------------------------------------------
|
|
-- Seth Henry 01/22/13 Design Start
|
|
-- Seth Henry 04/10/20 Code & comment cleanup
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 74... |
Line 116... |
architecture behave of o8_hd44780_4b is
|
architecture behave of o8_hd44780_4b is
|
|
|
constant User_Addr : std_logic_vector(15 downto 2)
|
constant User_Addr : std_logic_vector(15 downto 2)
|
:= Address(15 downto 2);
|
:= Address(15 downto 2);
|
alias Comp_Addr is Bus_Address(15 downto 2);
|
alias Comp_Addr is Bus_Address(15 downto 2);
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic := '0';
|
|
|
alias Reg_Addr is Bus_Address(1 downto 0);
|
alias Reg_Addr is Bus_Address(1 downto 0);
|
signal Reg_Addr_q : std_logic_vector(1 downto 0);
|
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
|
|
|
signal Wr_En : std_logic;
|
signal Wr_En : std_logic := '0';
|
signal Wr_Data_q : DATA_TYPE;
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic;
|
signal Rd_En : std_logic := '0';
|
|
|
signal Reg_Valid : std_logic;
|
signal Reg_Valid : std_logic := '0';
|
signal Reg_Sel : std_logic;
|
signal Reg_Sel : std_logic := '0';
|
signal Reg_Data : std_logic_vector(7 downto 0);
|
signal Reg_Data : std_logic_vector(7 downto 0) := x"00";
|
|
|
signal Tx_Ready : std_logic;
|
signal Tx_Ready : std_logic := '0';
|
|
|
--------------------------------------------------------------------------------
|
|
-- LCD Controller
|
|
--------------------------------------------------------------------------------
|
|
|
|
-- Register Map
|
|
-- Address Function
|
|
-- Offset Bitfield Description Read/Write
|
|
-- 0x0 AAAAAAAA LCD Register Write (Write-only)
|
|
-- 0x1 AAAAAAAA LCD Data Write (Write-only)
|
|
-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
|
|
-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
|
|
|
|
-- LCD Instruction Set
|
|
-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
|
|
------------------------------------------------------------------------
|
|
-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
|
|
-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
|
|
-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
|
|
-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
|
|
-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
|
|
-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
|
|
-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
|
|
-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
|
|
|
|
-- Notes:
|
|
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
|
|
-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
|
|
-- D = Display On/Off (1 = on, 0 = off)
|
|
-- C = Cursor On/Off (1 = on, 0 = off)
|
|
-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
|
|
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
|
|
-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
|
|
-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
|
|
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 0 in this module
|
|
-- A = Address (see data sheet for usage)
|
|
|
|
constant LCD_CONFIG1 : std_logic_vector(7 downto 4) := x"3"; -- Init to 4-bit mode
|
constant LCD_CONFIG1 : std_logic_vector(7 downto 4) := x"3"; -- Init to 4-bit mode
|
constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
|
constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
|
constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
|
constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
|
constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
|
constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
|
constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
|
constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
|
constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
|
constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
|
constant LCD_CONFIG7 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
|
constant LCD_CONFIG7 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
|
|
|
signal init_count : std_logic_vector(2 downto 0);
|
signal init_count : std_logic_vector(2 downto 0) := (others => '0');
|
|
|
constant INIT_40MS : integer := 40000;
|
constant INIT_40MS : integer := 40000;
|
constant INIT_BITS : integer := ceil_log2(INIT_40MS);
|
constant INIT_BITS : integer := ceil_log2(INIT_40MS);
|
constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
|
constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
|
conv_std_logic_vector(INIT_40MS,INIT_BITS);
|
conv_std_logic_vector(INIT_40MS,INIT_BITS);
|
| Line 159... |
Line 165... |
constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
|
constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
|
constant SNH_BITS : integer := ceil_log2(SNH_600NS);
|
constant SNH_BITS : integer := ceil_log2(SNH_600NS);
|
constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
|
constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
|
conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
|
conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
|
|
|
signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0);
|
signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) :=
|
|
(others => '0');
|
|
|
type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
|
type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
|
INIT_WAIT, FN_JUMP, IDLE,
|
INIT_WAIT, FN_JUMP, IDLE,
|
WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
|
WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
|
BUSY_PREP, BUSY_WAIT,
|
BUSY_PREP, BUSY_WAIT,
|
ISSUE_INT );
|
ISSUE_INT );
|
|
|
signal io_state : IO_STATES;
|
signal io_state : IO_STATES := INIT;
|
|
|
signal LCD_Data : std_logic_vector(7 downto 0);
|
signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
|
signal LCD_Addr : std_logic;
|
signal LCD_Addr : std_logic := '0';
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight signals
|
-- Backlight & Contrast signals
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
-- Do not adjust alone! DELTA constants must be
|
-- Do not adjust alone! DELTA constants must be
|
-- changed as well.
|
-- changed as well.
|
constant DAC_Width : integer := 8;
|
constant DAC_Width : integer := 8;
|
| Line 225... |
Line 232... |
constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
|
conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
|
|
|
constant CB : integer := ceil_log2(DIV_WIDTH);
|
constant CB : integer := ceil_log2(DIV_WIDTH);
|
|
|
signal LCD_Contrast : std_logic_vector(7 downto 0);
|
signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
|
|
|
|
signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal CN_DACin : std_logic_vector(DAC_WIDTH-1 downto 0);
|
signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
|
signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
|
signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
|
|
signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
|
signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
signal CN_diff : std_logic_vector(DIV_WIDTH downto 0);
|
|
|
|
signal CN_count : std_logic_vector(CB-1 downto 0);
|
signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
|
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
|
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
|
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
|
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
|
signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
|
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
|
|
|
|
signal LCD_Bright : std_logic_vector(7 downto 0);
|
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal BL_DACin : std_logic_vector(DAC_WIDTH-1 downto 0);
|
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
|
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
|
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
|
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
|
|
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
|
signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0);
|
|
|
|
signal BL_count : std_logic_vector(CB-1 downto 0);
|
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
|
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
|
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
|
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
|
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
|
|
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
|
|
begin
|
begin
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Open8 Register interface
|
-- Open8 Register interface
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
| Line 501... |
Line 509... |
Contrast_Enabled: if( Use_Contrast )generate
|
Contrast_Enabled: if( Use_Contrast )generate
|
|
|
CN_diff <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
CN_diff <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
('0' & CN_Divisor);
|
('0' & CN_Divisor);
|
|
|
CN_Dividend<= PADJ_2 when CN_DACin >= DELTA_2_I and CN_DACin < DELTA_3_I else
|
CN_Dividend<= PADJ_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
PADJ_3 when CN_DACin >= DELTA_3_I and CN_DACin < DELTA_4_I else
|
PADJ_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
PADJ_4 when CN_DACin >= DELTA_4_I and CN_DACin < DELTA_5_I else
|
PADJ_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
PADJ_5 when CN_DACin >= DELTA_5_I and CN_DACin < DELTA_6_I else
|
PADJ_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
PADJ_6 when CN_DACin >= DELTA_6_I else
|
PADJ_6 when CN_DACin_q >= DELTA_6_I else
|
PADJ_1;
|
PADJ_1;
|
|
|
CN_Next_Wdt<= DELTA_1 when CN_DACin >= DELTA_1_I and CN_DACin < DELTA_2_I else
|
CN_Next_Wdt<= DELTA_1 when CN_DACin_q >= DELTA_1_I and CN_DACin_q < DELTA_2_I else
|
DELTA_2 when CN_DACin >= DELTA_2_I and CN_DACin < DELTA_3_I else
|
DELTA_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
DELTA_3 when CN_DACin >= DELTA_3_I and CN_DACin < DELTA_4_I else
|
DELTA_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
DELTA_4 when CN_DACin >= DELTA_4_I and CN_DACin < DELTA_5_I else
|
DELTA_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
DELTA_5 when CN_DACin >= DELTA_5_I and CN_DACin < DELTA_6_I else
|
DELTA_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
DELTA_6 when CN_DACin >= DELTA_6_I else
|
DELTA_6 when CN_DACin_q >= DELTA_6_I else
|
(others => '0');
|
(others => '0');
|
|
|
CN_Next_Per <= BL_q(7 downto 0) - 1;
|
CN_Next_Per <= BL_q(7 downto 0) - 1;
|
|
|
CN_vDSM_proc: process( Clock, Reset )
|
CN_vDSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
CN_q <= (others => '0');
|
CN_q <= (others => '0');
|
CN_count <= (others => '1');
|
CN_count <= (others => '1');
|
CN_Divisor <= (others => '0');
|
CN_Divisor <= (others => '0');
|
CN_DACin <= (others => '0');
|
CN_DACin_q <= (others => '0');
|
CN_PWM_Wdt <= (others => '0');
|
CN_PWM_Wdt <= (others => '0');
|
CN_PWM_Per <= (others => '0');
|
CN_PWM_Per <= (others => '0');
|
CN_Per_Ctr <= (others => '0');
|
CN_Per_Ctr <= (others => '0');
|
CN_Wdt_Ctr <= (others => '0');
|
CN_Wdt_Ctr <= (others => '0');
|
LCD_CN <= '0';
|
LCD_CN <= '0';
|
| Line 541... |
Line 549... |
|
|
CN_count <= CN_count + 1;
|
CN_count <= CN_count + 1;
|
if( CN_count = DIV_WIDTH )then
|
if( CN_count = DIV_WIDTH )then
|
CN_PWM_Wdt <= CN_Next_Wdt;
|
CN_PWM_Wdt <= CN_Next_Wdt;
|
CN_PWM_Per <= CN_Next_Per;
|
CN_PWM_Per <= CN_Next_Per;
|
CN_DACin <= LCD_Contrast;
|
CN_DACin_q <= LCD_Contrast;
|
CN_Divisor <= (others => '0');
|
CN_Divisor <= (others => '0');
|
CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin;
|
CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin_q;
|
CN_q <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
|
CN_q <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
|
CN_count <= (others => '0');
|
CN_count <= (others => '0');
|
end if;
|
end if;
|
|
|
CN_Per_Ctr <= CN_Per_Ctr - 1;
|
CN_Per_Ctr <= CN_Per_Ctr - 1;
|
| Line 579... |
Line 587... |
Backlight_Enabled: if( Use_Backlight )generate
|
Backlight_Enabled: if( Use_Backlight )generate
|
|
|
BL_diff <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
BL_diff <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
('0' & BL_Divisor);
|
('0' & BL_Divisor);
|
|
|
BL_Dividend<= PADJ_2 when BL_DACin >= DELTA_2_I and BL_DACin < DELTA_3_I else
|
BL_Dividend<= PADJ_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
|
PADJ_3 when BL_DACin >= DELTA_3_I and BL_DACin < DELTA_4_I else
|
PADJ_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
|
PADJ_4 when BL_DACin >= DELTA_4_I and BL_DACin < DELTA_5_I else
|
PADJ_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
|
PADJ_5 when BL_DACin >= DELTA_5_I and BL_DACin < DELTA_6_I else
|
PADJ_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
|
PADJ_6 when BL_DACin >= DELTA_6_I else
|
PADJ_6 when BL_DACin_q >= DELTA_6_I else
|
PADJ_1;
|
PADJ_1;
|
|
|
BL_Next_Wdt<= DELTA_1 when BL_DACin >= DELTA_1_I and BL_DACin < DELTA_2_I else
|
BL_Next_Wdt<= DELTA_1 when BL_DACin_q >= DELTA_1_I and BL_DACin_q < DELTA_2_I else
|
DELTA_2 when BL_DACin >= DELTA_2_I and BL_DACin < DELTA_3_I else
|
DELTA_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
|
DELTA_3 when BL_DACin >= DELTA_3_I and BL_DACin < DELTA_4_I else
|
DELTA_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
|
DELTA_4 when BL_DACin >= DELTA_4_I and BL_DACin < DELTA_5_I else
|
DELTA_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
|
DELTA_5 when BL_DACin >= DELTA_5_I and BL_DACin < DELTA_6_I else
|
DELTA_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
|
DELTA_6 when BL_DACin >= DELTA_6_I else
|
DELTA_6 when BL_DACin_q >= DELTA_6_I else
|
(others => '0');
|
(others => '0');
|
|
|
BL_Next_Per <= BL_q(7 downto 0) - 1;
|
BL_Next_Per <= BL_q(7 downto 0) - 1;
|
|
|
BL_vDSM_proc: process( Clock, Reset )
|
BL_vDSM_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
BL_q <= (others => '0');
|
BL_q <= (others => '0');
|
BL_count <= (others => '1');
|
BL_count <= (others => '1');
|
BL_Divisor <= (others => '0');
|
BL_Divisor <= (others => '0');
|
BL_DACin <= (others => '0');
|
BL_DACin_q <= (others => '0');
|
BL_PWM_Wdt <= (others => '0');
|
BL_PWM_Wdt <= (others => '0');
|
BL_PWM_Per <= (others => '0');
|
BL_PWM_Per <= (others => '0');
|
BL_Per_Ctr <= (others => '0');
|
BL_Per_Ctr <= (others => '0');
|
BL_Wdt_Ctr <= (others => '0');
|
BL_Wdt_Ctr <= (others => '0');
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
| Line 619... |
Line 627... |
|
|
BL_count <= BL_count + 1;
|
BL_count <= BL_count + 1;
|
if( BL_count = DIV_WIDTH )then
|
if( BL_count = DIV_WIDTH )then
|
BL_PWM_Wdt <= BL_Next_Wdt;
|
BL_PWM_Wdt <= BL_Next_Wdt;
|
BL_PWM_Per <= BL_Next_Per;
|
BL_PWM_Per <= BL_Next_Per;
|
BL_DACin <= LCD_Bright;
|
BL_DACin_q <= LCD_Bright;
|
BL_Divisor <= (others => '0');
|
BL_Divisor <= (others => '0');
|
BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin;
|
BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin_q;
|
BL_q <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
|
BL_q <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
|
BL_count <= (others => '0');
|
BL_count <= (others => '0');
|
end if;
|
end if;
|
|
|
BL_Per_Ctr <= BL_Per_Ctr - 1;
|
BL_Per_Ctr <= BL_Per_Ctr - 1;
|
