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Line 70... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 85... |
Line 86... |
generic(
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generic(
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Use_Contrast : boolean;
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Use_Contrast : boolean;
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Default_Contrast : std_logic_vector(7 downto 0);
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Default_Contrast : std_logic_vector(7 downto 0);
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Use_Backlight : boolean;
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Use_Backlight : boolean;
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Default_Brightness : std_logic_vector(7 downto 0);
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Default_Brightness : std_logic_vector(7 downto 0);
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Address : ADDRESS_TYPE;
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Clock_Frequency : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Sys_Freq : real
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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uSec_Tick : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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| Line 110... |
Line 105... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_hd44780_4b is
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architecture behave of o8_hd44780_4b is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
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constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
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constant SNH_600NS : integer := integer(Clock_Frequency * 0.000000600);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) :=
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) :=
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