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architecture behave of o8_hd44780_8b is
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architecture behave of o8_hd44780_8b is
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Addr_q : std_logic_vector(1 downto 0);
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signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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signal Reg_Valid : std_logic;
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signal Reg_Valid : std_logic := '0';
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signal Reg_Sel : std_logic;
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signal Reg_Sel : std_logic := '0';
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signal Reg_Data : std_logic_vector(7 downto 0);
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signal Reg_Data : DATA_TYPE := x"00";
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signal Tx_Ready : std_logic;
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signal Tx_Ready : std_logic;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD Controller
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-- LCD Controller
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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signal init_count : std_logic_vector(2 downto 0);
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signal init_count : std_logic_vector(2 downto 0) := (others => '0');
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constant INIT_40MS : integer := 40000;
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constant INIT_40MS : integer := 40000;
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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Line 127... |
-- most instructions completing in 37uS. No clue as to why, but it works
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-- most instructions completing in 37uS. No clue as to why, but it works
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constant BUSY_50US : integer := 50;
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constant BUSY_50US : integer := 50;
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
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constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
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constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0);
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
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type IO_STATES is (INIT, FN_JUMP, IDLE,
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type IO_STATES is (INIT, FN_JUMP, IDLE,
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WR_PREP, WR_SETUP, WR_HOLD,
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WR_PREP, WR_SETUP, WR_HOLD,
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BUSY_PREP, BUSY_WAIT,
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BUSY_PREP, BUSY_WAIT,
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ISSUE_INT );
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ISSUE_INT );
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signal io_state : IO_STATES;
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signal io_state : IO_STATES;
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signal LCD_Data : std_logic_vector(7 downto 0);
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signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
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signal LCD_Addr : std_logic;
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signal LCD_Addr : std_logic := '0';
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Backlight & Contrast signals
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-- Backlight & Contrast signals
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal LCD_Contrast : std_logic_vector(7 downto 0);
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signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
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signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0);
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signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
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signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
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signal CN_diff : std_logic_vector(DIV_WIDTH downto 0);
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signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
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signal CN_count : std_logic_vector(CB-1 downto 0);
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signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
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signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal LCD_Bright : std_logic_vector(7 downto 0);
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signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
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signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0);
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signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
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signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
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signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
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signal BL_diff : std_logic_vector(DIV_WIDTH downto 0);
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signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
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signal BL_count : std_logic_vector(CB-1 downto 0);
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signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
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signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
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begin
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begin
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Open8 Register interface
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-- Open8 Register interface
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| Line 255... |
Line 255... |
if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Reg_Data <= x"00";
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Reg_Data <= x"00";
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| Line 285... |
Line 285... |
LCD_Bright <= Wr_Data_q;
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LCD_Bright <= Wr_Data_q;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Rd_Data(7) <= Tx_Ready;
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Rd_Data(7) <= Tx_Ready;
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