| Line 171... |
Line 171... |
WR_PREP, WR_SETUP, WR_HOLD,
|
WR_PREP, WR_SETUP, WR_HOLD,
|
BUSY_PREP, BUSY_WAIT,
|
BUSY_PREP, BUSY_WAIT,
|
ISSUE_INT );
|
ISSUE_INT );
|
signal io_state : IO_STATES;
|
signal io_state : IO_STATES;
|
|
|
signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
|
signal LCD_Data : DATA_TYPE := x"00";
|
signal LCD_Addr : std_logic := '0';
|
signal LCD_Addr : std_logic := '0';
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight & Contrast signals
|
-- Backlight & Contrast signals
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
-- Do not adjust alone! DELTA constants must be
|
signal LCD_Contrast : DATA_TYPE := x"00";
|
-- changed as well.
|
signal LCD_Bright : DATA_TYPE := x"00";
|
constant DAC_Width : integer := 8;
|
|
|
|
constant DELTA_1_I : integer := 1;
|
|
constant DELTA_2_I : integer := 5;
|
|
constant DELTA_3_I : integer := 25;
|
|
constant DELTA_4_I : integer := 75;
|
|
constant DELTA_5_I : integer := 125;
|
|
constant DELTA_6_I : integer := 195;
|
|
|
|
constant DELTA_1 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_1_I, DAC_Width);
|
|
constant DELTA_2 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_2_I, DAC_Width);
|
|
constant DELTA_3 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_3_I, DAC_Width);
|
|
constant DELTA_4 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_4_I, DAC_Width);
|
|
constant DELTA_5 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_5_I, DAC_Width);
|
|
constant DELTA_6 : std_logic_vector(DAC_Width-1 downto 0) :=
|
|
conv_std_logic_vector(DELTA_6_I, DAC_Width);
|
|
|
|
constant MAX_PERIOD : integer := 2**DAC_Width;
|
|
constant DIV_WIDTH : integer := DAC_Width * 2;
|
|
|
|
constant PADJ_1_I : integer := DELTA_1_I * MAX_PERIOD;
|
|
constant PADJ_2_I : integer := DELTA_2_I * MAX_PERIOD;
|
|
constant PADJ_3_I : integer := DELTA_3_I * MAX_PERIOD;
|
|
constant PADJ_4_I : integer := DELTA_4_I * MAX_PERIOD;
|
|
constant PADJ_5_I : integer := DELTA_5_I * MAX_PERIOD;
|
|
constant PADJ_6_I : integer := DELTA_6_I * MAX_PERIOD;
|
|
|
|
constant PADJ_1 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
|
|
constant PADJ_2 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
|
|
constant PADJ_3 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
|
|
constant PADJ_4 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
|
|
constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
|
|
constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
|
|
conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
|
|
|
|
constant CB : integer := ceil_log2(DIV_WIDTH);
|
|
|
|
signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
|
|
|
|
signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
|
|
|
signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
|
|
signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
|
signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
|
|
|
signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
|
|
|
signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
|
|
|
|
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
|
|
|
|
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
|
|
|
|
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
|
|
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
|
|
|
|
signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
|
|
|
|
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
|
|
|
|
begin
|
begin
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Open8 Register interface
|
-- Open8 Register interface
|
| Line 454... |
Line 366... |
LCD_CN <= '0';
|
LCD_CN <= '0';
|
end generate;
|
end generate;
|
|
|
Contrast_Enabled: if( Use_Contrast )generate
|
Contrast_Enabled: if( Use_Contrast )generate
|
|
|
CN_diff <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
U_CN : entity work.vdsm8
|
('0' & CN_Divisor);
|
generic map(
|
|
Reset_Level => Reset_Level
|
CN_Dividend<= PADJ_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
)
|
PADJ_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
port map(
|
PADJ_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
Clock => Clock,
|
PADJ_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
Reset => Reset,
|
PADJ_6 when CN_DACin_q >= DELTA_6_I else
|
DACin => LCD_Contrast,
|
PADJ_1;
|
DACout => LCD_CN
|
|
);
|
CN_Next_Wdt<= DELTA_1 when CN_DACin_q >= DELTA_1_I and CN_DACin_q < DELTA_2_I else
|
|
DELTA_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
|
|
DELTA_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
|
|
DELTA_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
|
|
DELTA_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
|
|
DELTA_6 when CN_DACin_q >= DELTA_6_I else
|
|
(others => '0');
|
|
|
|
CN_Next_Per <= BL_q(7 downto 0) - 1;
|
|
|
|
CN_vDSM_proc: process( Clock, Reset )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
CN_q <= (others => '0');
|
|
CN_count <= (others => '1');
|
|
CN_Divisor <= (others => '0');
|
|
CN_DACin_q <= (others => '0');
|
|
CN_PWM_Wdt <= (others => '0');
|
|
CN_PWM_Per <= (others => '0');
|
|
CN_Per_Ctr <= (others => '0');
|
|
CN_Wdt_Ctr <= (others => '0');
|
|
LCD_CN <= '0';
|
|
elsif( rising_edge(Clock) )then
|
|
CN_q <= CN_diff(DIV_WIDTH-1 downto 0) &
|
|
CN_q(DIV_WIDTH-2 downto 0) & '1';
|
|
if( CN_diff(DIV_WIDTH) = '1' )then
|
|
CN_q <= CN_q(DIV_WIDTH*2-2 downto 0) & '0';
|
|
end if;
|
|
|
|
CN_count <= CN_count + 1;
|
|
if( CN_count = DIV_WIDTH )then
|
|
CN_PWM_Wdt <= CN_Next_Wdt;
|
|
CN_PWM_Per <= CN_Next_Per;
|
|
CN_DACin_q <= LCD_Contrast;
|
|
CN_Divisor <= (others => '0');
|
|
CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin_q;
|
|
CN_q <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
|
|
CN_count <= (others => '0');
|
|
end if;
|
|
|
|
CN_Per_Ctr <= CN_Per_Ctr - 1;
|
|
CN_Wdt_Ctr <= CN_Wdt_Ctr - 1;
|
|
|
|
LCD_CN <= '1';
|
|
if( CN_Wdt_Ctr = 0 )then
|
|
LCD_CN <= '0';
|
|
CN_Wdt_Ctr <= (others => '0');
|
|
end if;
|
|
|
|
if( CN_Per_Ctr = 0 )then
|
|
CN_Per_Ctr <= CN_PWM_Per;
|
|
CN_Wdt_Ctr <= CN_PWM_Wdt;
|
|
end if;
|
|
|
|
end if;
|
|
end process;
|
|
end generate;
|
end generate;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight control logic (optional)
|
-- Backlight control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
| Line 532... |
Line 389... |
LCD_BL <= '0';
|
LCD_BL <= '0';
|
end generate;
|
end generate;
|
|
|
Backlight_Enabled: if( Use_Backlight )generate
|
Backlight_Enabled: if( Use_Backlight )generate
|
|
|
BL_diff <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
|
U_BL : entity work.vdsm8
|
('0' & BL_Divisor);
|
generic map(
|
|
Reset_Level => Reset_Level
|
BL_Dividend<= PADJ_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
|
)
|
PADJ_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
|
port map(
|
PADJ_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
|
Clock => Clock,
|
PADJ_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
|
Reset => Reset,
|
PADJ_6 when BL_DACin_q >= DELTA_6_I else
|
DACin => LCD_Bright,
|
PADJ_1;
|
DACout => LCD_BL
|
|
);
|
BL_Next_Wdt<= DELTA_1 when BL_DACin_q >= DELTA_1_I and BL_DACin_q < DELTA_2_I else
|
|
DELTA_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
|
|
DELTA_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
|
|
DELTA_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
|
|
DELTA_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
|
|
DELTA_6 when BL_DACin_q >= DELTA_6_I else
|
|
(others => '0');
|
|
|
|
BL_Next_Per <= BL_q(7 downto 0) - 1;
|
|
|
|
BL_vDSM_proc: process( Clock, Reset )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
BL_q <= (others => '0');
|
|
BL_count <= (others => '1');
|
|
BL_Divisor <= (others => '0');
|
|
BL_DACin_q <= (others => '0');
|
|
BL_PWM_Wdt <= (others => '0');
|
|
BL_PWM_Per <= (others => '0');
|
|
BL_Per_Ctr <= (others => '0');
|
|
BL_Wdt_Ctr <= (others => '0');
|
|
LCD_BL <= '0';
|
|
elsif( rising_edge(Clock) )then
|
|
BL_q <= BL_diff(DIV_WIDTH-1 downto 0) &
|
|
BL_q(DIV_WIDTH-2 downto 0) & '1';
|
|
if( BL_diff(DIV_WIDTH) = '1' )then
|
|
BL_q <= BL_q(DIV_WIDTH*2-2 downto 0) & '0';
|
|
end if;
|
|
|
|
BL_count <= BL_count + 1;
|
|
if( BL_count = DIV_WIDTH )then
|
|
BL_PWM_Wdt <= BL_Next_Wdt;
|
|
BL_PWM_Per <= BL_Next_Per;
|
|
BL_DACin_q <= LCD_Bright;
|
|
BL_Divisor <= (others => '0');
|
|
BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin_q;
|
|
BL_q <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
|
|
BL_count <= (others => '0');
|
|
end if;
|
|
|
|
BL_Per_Ctr <= BL_Per_Ctr - 1;
|
|
BL_Wdt_Ctr <= BL_Wdt_Ctr - 1;
|
|
|
|
LCD_BL <= '1';
|
|
if( BL_Wdt_Ctr = 0 )then
|
|
LCD_BL <= '0';
|
|
BL_Wdt_Ctr <= (others => '0');
|
|
end if;
|
|
|
|
if( BL_Per_Ctr = 0 )then
|
|
BL_Per_Ctr <= BL_PWM_Per;
|
|
BL_Wdt_Ctr <= BL_PWM_Wdt;
|
|
end if;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
end generate;
|
end generate;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
