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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_8b.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 70... Line 70...
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      01/22/13 Design Start
-- Seth Henry      01/22/13 Design Start
-- Seth Henry      04/10/20 Code & comment cleanup
-- Seth Henry      04/10/20 Code & comment cleanup
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 85... Line 86...
generic(
generic(
  Use_Contrast          : boolean;
  Use_Contrast          : boolean;
  Default_Contrast      : std_logic_vector(7 downto 0);
  Default_Contrast      : std_logic_vector(7 downto 0);
  Use_Backlight         : boolean;
  Use_Backlight         : boolean;
  Default_Brightness    : std_logic_vector(7 downto 0);
  Default_Brightness    : std_logic_vector(7 downto 0);
  Address               : ADDRESS_TYPE;
  Clock_Frequency       : real;
  Reset_Level           : std_logic;
  Address               : ADDRESS_TYPE
  Sys_Freq              : real
 
);
);
port(
port(
  Clock                 : in  std_logic;
 
  Reset                 : in  std_logic;
 
  uSec_Tick             : in  std_logic;
 
  --
 
  Open8_Bus             : in  OPEN8_BUS_TYPE;
  Open8_Bus             : in  OPEN8_BUS_TYPE;
  Rd_Data               : out DATA_TYPE;
  Rd_Data               : out DATA_TYPE;
  Interrupt             : out std_logic;
  Interrupt             : out std_logic;
  --
  --
  LCD_E                 : out std_logic;
  LCD_E                 : out std_logic;
Line 109... Line 105...
);
);
end entity;
end entity;
 
 
architecture behave of o8_hd44780_8b is
architecture behave of o8_hd44780_8b is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : std_logic_vector(15 downto 2)
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
 
 
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  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
 
 
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
 
 
  constant SNH_600NS         : integer := integer(Sys_Freq * 0.000000600);
  constant SNH_600NS         : integer := integer(Clock_Frequency * 0.000000600);
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
 
 
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');

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