OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_8b.vhd] - Diff between revs 224 and 244

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 224 Rev 244
Line 71... Line 71...
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      01/22/13 Design Start
-- Seth Henry      01/22/13 Design Start
-- Seth Henry      04/10/20 Code & comment cleanup
-- Seth Henry      04/10/20 Code & comment cleanup
-- Seth Henry      04/16/20 Modified to use Open8 bus record
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 91... Line 92...
  Clock_Frequency       : real;
  Clock_Frequency       : real;
  Address               : ADDRESS_TYPE
  Address               : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus             : in  OPEN8_BUS_TYPE;
  Open8_Bus             : in  OPEN8_BUS_TYPE;
 
  Write_Qual            : in  std_logic := '1';
  Rd_Data               : out DATA_TYPE;
  Rd_Data               : out DATA_TYPE;
  Interrupt             : out std_logic;
  Interrupt             : out std_logic;
  --
  --
  LCD_E                 : out std_logic;
  LCD_E                 : out std_logic;
  LCD_RW                : out std_logic;
  LCD_RW                : out std_logic;
Line 112... Line 114...
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : std_logic_vector(15 downto 2)
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic;
 
 
  alias  Reg_Addr             is Open8_Bus.Address(1 downto 0);
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
  signal Reg_Addr_q          : std_logic_vector(1 downto 0) := (others => '0');
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
 
  signal Wr_En_d             : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Rd_En               : std_logic := '0';
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal Reg_Valid           : std_logic := '0';
  signal Reg_Valid           : std_logic := '0';
  signal Reg_Sel             : std_logic := '0';
  signal Reg_Sel             : std_logic := '0';
  signal Reg_Data            : DATA_TYPE := x"00";
  signal Reg_Data            : DATA_TYPE := x"00";
 
 
Line 185... Line 189...
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Open8 Register interface
-- Open8 Register interface
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Reg_Addr_q             <= (others => '0');
      Reg_Sel_q              <= "00";
      Wr_Data_q              <= (others => '0');
      Wr_En_q                <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      Reg_Valid              <= '0';
      Reg_Valid              <= '0';
      Reg_Sel                <= '0';
      Reg_Sel                <= '0';
      Reg_Data               <= x"00";
      Reg_Data               <= x"00";
 
 
      LCD_Contrast           <= Default_Contrast;
      LCD_Contrast           <= Default_Contrast;
      LCD_Bright             <= Default_Brightness;
      LCD_Bright             <= Default_Brightness;
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Reg_Addr_q             <= Reg_Addr;
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Wr_Data_q              <= Open8_Bus.Wr_Data;
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
 
 
 
 
      Wr_En_q                <= Wr_En_d;
 
      Wr_Data_q              <= Wr_Data_d;
      Reg_Valid              <= '0';
      Reg_Valid              <= '0';
 
      if( Wr_En_q = '1' )then
      if( Wr_En = '1' )then
        case( Reg_Sel_q )is
        case( Reg_Addr_q )is
 
          when "00" | "01" =>
          when "00" | "01" =>
            Reg_Valid        <= '1';
            Reg_Valid        <= '1';
            Reg_Sel          <= Reg_Addr_q(0);
            Reg_Sel          <= Reg_Sel_q(0);
            Reg_Data         <= Wr_Data_q;
            Reg_Data         <= Wr_Data_q;
          when "10" =>
          when "10" =>
            LCD_Contrast     <= Wr_Data_q;
            LCD_Contrast     <= Wr_Data_q;
          when "11" =>
          when "11" =>
            LCD_Bright       <= Wr_Data_q;
            LCD_Bright       <= Wr_Data_q;
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      if( Rd_En_q = '1' )then
      if( Rd_En = '1' )then
        case( Reg_Sel_q )is
        case( Reg_Addr_q )is
 
          when "00" | "01" =>
          when "00" | "01" =>
            Rd_Data(7)       <= Tx_Ready;
            Rd_Data(7)       <= Tx_Ready;
          when "10" =>
          when "10" =>
            Rd_Data          <= LCD_Contrast;
            Rd_Data          <= LCD_Contrast;
          when "11" =>
          when "11" =>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.