| Line 71... |
Line 71... |
-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 91... |
Line 92... |
Clock_Frequency : real;
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Clock_Frequency : real;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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| Line 112... |
Line 114... |
alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic;
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Data : DATA_TYPE := x"00";
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signal Reg_Data : DATA_TYPE := x"00";
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| Line 185... |
Line 189... |
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Open8 Register interface
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-- Open8 Register interface
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Addr_q <= (others => '0');
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Reg_Sel_q <= "00";
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Wr_Data_q <= (others => '0');
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Wr_En_q <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Reg_Data <= x"00";
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Reg_Data <= x"00";
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LCD_Contrast <= Default_Contrast;
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LCD_Contrast <= Default_Contrast;
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LCD_Bright <= Default_Brightness;
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LCD_Bright <= Default_Brightness;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Addr_q <= Reg_Addr;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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if( Wr_En_q = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Addr_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Reg_Valid <= '1';
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Reg_Valid <= '1';
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Reg_Sel <= Reg_Addr_q(0);
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Reg_Sel <= Reg_Sel_q(0);
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Reg_Data <= Wr_Data_q;
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Reg_Data <= Wr_Data_q;
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when "10" =>
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when "10" =>
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LCD_Contrast <= Wr_Data_q;
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LCD_Contrast <= Wr_Data_q;
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when "11" =>
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when "11" =>
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LCD_Bright <= Wr_Data_q;
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LCD_Bright <= Wr_Data_q;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Addr_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Rd_Data(7) <= Tx_Ready;
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Rd_Data(7) <= Tx_Ready;
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when "10" =>
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when "10" =>
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Rd_Data <= LCD_Contrast;
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Rd_Data <= LCD_Contrast;
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when "11" =>
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when "11" =>
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