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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_if.vhd] - Diff between revs 289 and 322

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Rev 289	Rev 322
Line 97...	Line 97...
`use work.open8_pkg.all;`	`use work.open8_pkg.all;`

`entity o8_hd44780_if is`	`entity o8_hd44780_if is`
`generic(`	`generic(`
`Use_4Bit_IF : boolean := FALSE;`	`Use_4Bit_IF : boolean := FALSE;`
`-- Bus IF timing`	`-- LCD bus IF timing`
`Tsu : integer := 40; -- ns`	`Tas : integer := 20; -- ns`
`Tpw : integer := 250; -- nS`	`Tpwe : integer := 450; -- nS`
`Tcyc : integer := 500; -- nS`	`Tcyce : integer := 1000; -- nS`
`-- Panel command timing`	`-- LCD command timing`
`Tpwrdly : integer := 40000; -- uS`	`Tpwrdly : integer := 40000; -- uS`
`Tcldsp : integer := 2000; -- uS`	`Tcldsp : integer := 2000; -- uS`
`Tbusy : integer := 50; -- uS`	`Tbusy : integer := 50; -- uS`
`-- Contrast/Backlight`	`-- Backlight`
`Use_Backlight : boolean := FALSE;`	`Use_Backlight : boolean := FALSE;`
`Default_Brightness : std_logic_vector(7 downto 0) := x"00";`	`Default_Brightness : std_logic_vector(7 downto 0) := x"00";`
	`-- System clock & address`
`Clock_Frequency : real;`	`Clock_Frequency : real;`
`Address : ADDRESS_TYPE`	`Address : ADDRESS_TYPE`
`);`	`);`
`port(`	`port(`
`Open8_Bus : in OPEN8_BUS_TYPE;`	`Open8_Bus : in OPEN8_BUS_TYPE;`
Line 336...	Line 337...

`IF_Type_4bit: if( Use_4Bit_IF )generate`	`IF_Type_4bit: if( Use_4Bit_IF )generate`

`U_IO : entity work.hd44780_4b`	`U_IO : entity work.hd44780_4b`
`generic map(`	`generic map(`
`Tsu => Tsu,`	`Tas => Tas,`
`Tpw => Tpw,`	`Tpwe => Tpwe,`
`Tcyc => Tcyc,`	`Tcyce => Tcyce,`
`Clock_Frequency => Clock_Frequency,`	`Clock_Frequency => Clock_Frequency,`
`Reset_Level => Reset_Level`	`Reset_Level => Reset_Level`
`)`	`)`
`port map(`	`port map(`
`Clock => Clock,`	`Clock => Clock,`
Line 364...	Line 365...

`IF_Type_8bit: if( not Use_4Bit_IF )generate`	`IF_Type_8bit: if( not Use_4Bit_IF )generate`

`U_IO : entity work.hd44780_8b`	`U_IO : entity work.hd44780_8b`
`generic map(`	`generic map(`
`Tsu => Tsu,`	`Tas => Tas,`
`Tpw => Tpw,`	`Tpwe => Tpwe,`
`Tcyc => Tcyc,`	`Tcyce => Tcyce,`
`Clock_Frequency => Clock_Frequency,`	`Clock_Frequency => Clock_Frequency,`
`Reset_Level => Reset_Level`	`Reset_Level => Reset_Level`
`)`	`)`
`port map(`	`port map(`
`Clock => Clock,`	`Clock => Clock,`

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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_if.vhd] - Diff between revs 289 and 322