| Line 49... |
Line 49... |
);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Enable : in std_logic;
|
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Rd_Data : out DATA_TYPE
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Rd_Data : out DATA_TYPE
|
);
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);
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end entity;
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end entity;
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|
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architecture behave of o8_lfsr32 is
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architecture behave of o8_lfsr32 is
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|
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constant User_Addr : std_logic_vector(15 downto 1)
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constant User_Addr : std_logic_vector(15 downto 1)
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:= Address(15 downto 1);
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:= Address(15 downto 1);
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alias Comp_Addr is Bus_Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Reg_Sel is Bus_Address(0);
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alias Reg_Sel is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Reg_Sel_q : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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|
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signal d0 : std_logic := '0';
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signal d0 : std_logic := '0';
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
|
|
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begin
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begin
|
|
|
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
|
|
'0';
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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|
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lfsr_proc: process( Clock, Reset )
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lfsr_proc: process( Clock, Reset )
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begin
|
begin
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if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
