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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_lfsr32.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 59... Line 59...
  alias Reset                is Open8_Bus.Reset;
  alias Reset                is Open8_Bus.Reset;
 
 
  constant User_Addr         : std_logic_vector(15 downto 1)
  constant User_Addr         : std_logic_vector(15 downto 1)
                               := Address(15 downto 1);
                               := Address(15 downto 1);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
  alias  Reg_Sel             is Open8_Bus.Address(0);
 
  signal Reg_Sel_q           : std_logic := '0';
 
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
  signal Rd_En               : std_logic := '0';
  alias  Reg_Sel_d           is Open8_Bus.Address(0);
 
  signal Reg_Sel_q           : std_logic := '0';
 
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal d0                  : std_logic := '0';
  signal d0                  : std_logic := '0';
  signal lfsr                : std_logic_vector(31 downto 0) := x"00000000";
  signal lfsr                : std_logic_vector(31 downto 0) := x"00000000";
  signal lfsr_q              : std_logic_vector(31 downto 0) := x"00000000";
  signal lfsr_q              : std_logic_vector(31 downto 0) := x"00000000";
 
 
begin
begin
 
 
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
                                '0';
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  d0                         <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
  d0                         <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
 
 
  lfsr_proc: process( Clock, Reset )
  lfsr_proc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Reg_Sel_q              <= '0';
      Reg_Sel_q              <= '0';
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= x"00";
      Rd_Data                <= x"00";
      lfsr                   <= Init_Seed;
      lfsr                   <= Init_Seed;
      lfsr_q                 <= x"00000000";
      lfsr_q                 <= x"00000000";
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Rd_Data                <= x"00";
      Reg_Sel_q              <= Reg_Sel_d;
      Reg_Sel_q              <= Reg_Sel;
 
      Rd_En                  <= Addr_Match;
      Rd_En_q                <= Rd_En_d;
      if( Rd_En = '1' )then
      Rd_Data                <= OPEN8_NULLBUS;
 
      if( Rd_En_q = '1' )then
        Rd_Data              <= lfsr_q(31 downto 24);
        Rd_Data              <= lfsr_q(31 downto 24);
        lfsr_q               <= lfsr_q(23 downto 0) & x"00";
        lfsr_q               <= lfsr_q(23 downto 0) & x"00";
        if( Reg_Sel_q = '1' )then
        if( Reg_Sel_q = '1' )then
          Rd_Data            <= lfsr_q(31) & "0000000";
          Rd_Data            <= lfsr_q(31) & "0000000";
          lfsr_q             <= lfsr_q(30 downto 0) & '0';
          lfsr_q             <= lfsr_q(30 downto 0) & '0';

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