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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 1)
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constant User_Addr : std_logic_vector(15 downto 1)
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:= Address(15 downto 1);
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:= Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Reg_Sel is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(0);
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signal Reg_Sel_q : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal d0 : std_logic := '0';
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signal d0 : std_logic := '0';
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
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signal lfsr_q : std_logic_vector(31 downto 0) := x"00000000";
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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'0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
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lfsr_proc: process( Clock, Reset )
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lfsr_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= '0';
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Reg_Sel_q <= '0';
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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lfsr <= Init_Seed;
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lfsr <= Init_Seed;
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lfsr_q <= x"00000000";
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lfsr_q <= x"00000000";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rd_Data <= x"00";
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel;
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Rd_En <= Addr_Match;
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Rd_En_q <= Rd_En_d;
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if( Rd_En = '1' )then
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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Rd_Data <= lfsr_q(31 downto 24);
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Rd_Data <= lfsr_q(31 downto 24);
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lfsr_q <= lfsr_q(23 downto 0) & x"00";
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lfsr_q <= lfsr_q(23 downto 0) & x"00";
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if( Reg_Sel_q = '1' )then
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if( Reg_Sel_q = '1' )then
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Rd_Data <= lfsr_q(31) & "0000000";
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Rd_Data <= lfsr_q(31) & "0000000";
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lfsr_q <= lfsr_q(30 downto 0) & '0';
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lfsr_q <= lfsr_q(30 downto 0) & '0';
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