| Line 48... |
Line 48... |
);
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);
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port(
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port(
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Clock : in std_logic; -- 96MHz MAX for proper operation
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Clock : in std_logic; -- 96MHz MAX for proper operation
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Reset : in std_logic;
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Reset : in std_logic;
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uSec_Tick : in std_logic;
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uSec_Tick : in std_logic;
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-- Client IF
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--
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Bus_Address : in ADDRESS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- ADC IF
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-- ADC IF
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ADC_SCLK : out std_logic;
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ADC_SCLK : out std_logic;
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ADC_CONV : out std_logic;
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ADC_CONV : out std_logic;
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| Line 68... |
Line 65... |
architecture behave of o8_ltc2355_2p is
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architecture behave of o8_ltc2355_2p is
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|
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constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
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constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
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|
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constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Reg_Sel is Bus_Address(2 downto 0);
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alias Reg_Sel is Open8_Bus.Address(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE;
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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| Line 111... |
Line 108... |
Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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User_Trig <= '0';
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User_Trig <= '0';
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Timer_Int <= x"00";
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Timer_Int <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel;
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Reg_Sel_q <= Reg_Sel;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En <= Wr_Enable and Addr_Match;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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User_Trig <= '0';
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User_Trig <= '0';
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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if( Reg_Sel_q = "110" )then
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if( Reg_Sel_q = "110" )then
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Timer_Int <= Wr_Data_q;
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Timer_Int <= Wr_Data_q;
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end if;
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end if;
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if( Reg_Sel_q = "111" )then
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if( Reg_Sel_q = "111" )then
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User_Trig <= '1';
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User_Trig <= '1';
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end if;
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end if;
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end if;
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end if;
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|
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Rd_En <= Rd_Enable and Addr_Match;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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|
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if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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-- Channel 1, Full resolution, lower byte
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-- Channel 1, Full resolution, lower byte
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