| Line 28... |
Line 28... |
-- : parallel data buses.
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-- : parallel data buses.
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--
|
--
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-- Notes : Depends on the fact that the two LTC2355 converters are wired
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-- Notes : Depends on the fact that the two LTC2355 converters are wired
|
-- : with their SCLK and CONV lines tied together, and DATA1 and
|
-- : with their SCLK and CONV lines tied together, and DATA1 and
|
-- : DATA2 independently routed to separate I/O pins.
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-- : DATA2 independently routed to separate I/O pins.
|
|
--
|
|
-- : Works best when the clock frequency is 96MHz or lower. Module
|
|
-- : will divide the clock by 2 if it is greater than this.
|
|
--
|
|
-- Revision History
|
|
-- Author Date Change
|
|
------------------ -------- ---------------------------------------------------
|
|
-- Seth Henry 04/16/20 Revision block added
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|
|
library ieee;
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library ieee;
|
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
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| Line 40... |
Line 48... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
|
|
|
entity o8_ltc2355_2p is
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entity o8_ltc2355_2p is
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generic(
|
generic(
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Address : ADDRESS_TYPE;
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Clock_Frequency : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Sys_Freq : real
|
|
);
|
);
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port(
|
port(
|
Clock : in std_logic; -- 96MHz MAX for proper operation
|
|
Reset : in std_logic;
|
|
uSec_Tick : in std_logic;
|
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--
|
|
Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- ADC IF
|
-- ADC IF
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ADC_SCLK : out std_logic;
|
ADC_SCLK : out std_logic;
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| Line 62... |
Line 65... |
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_ltc2355_2p is
|
architecture behave of o8_ltc2355_2p is
|
|
|
constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
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alias Clock is Open8_Bus.Clock;
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|
alias Reset is Open8_Bus.Reset;
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|
alias uSec_Tick is Open8_Bus.uSec_Tick;
|
|
|
|
constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
|
|
|
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Reg_Sel is Open8_Bus.Address(2 downto 0);
|
alias Reg_Sel is Open8_Bus.Address(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
|
signal Reg_Sel_q : std_logic_vector(2 downto 0);
|
