| Line 19... |
Line 19... |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- VHDL units : ltc2355_2p
|
-- VHDL units : o8_ltc2355_2p
|
-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with
|
-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with
|
-- : common clock and CONVERT START inputs. Because they are
|
-- : common clock and CONVERT START inputs. Because they are
|
-- : synchronized, this entity provides simultaneously updated
|
-- : synchronized, this entity provides simultaneously updated
|
-- : parallel data buses.
|
-- : parallel data buses.
|
--
|
--
|
| Line 32... |
Line 32... |
-- : DATA2 independently routed to separate I/O pins.
|
-- : DATA2 independently routed to separate I/O pins.
|
--
|
--
|
-- : Works best when the clock frequency is 96MHz or lower. Module
|
-- : Works best when the clock frequency is 96MHz or lower. Module
|
-- : will divide the clock by 2 if it is greater than this.
|
-- : will divide the clock by 2 if it is greater than this.
|
--
|
--
|
|
-- Register Map:
|
|
-- Offset Bitfield Description Read/Write
|
|
-- 0x0 AAAAAAAA ADC Channel 1 Data(7:0) (RO)
|
|
-- 0x1 --AAAAAA ADC Channel 1 Data(13:8) (RO)
|
|
-- 0x2 AAAAAAAA ADC Channel 2 Data(7:0) (RO)
|
|
-- 0x3 --AAAAAA ADC Channel 2 Data(13:8) (reduced) (RO)
|
|
-- 0x4 AAAAAAAA ADC Channel 1 Data(13:6) (reduced) (RO)
|
|
-- 0x5 AAAAAAAA ADC Channel 2 Data(13:6) (RO)
|
|
-- 0x6 AAAAAAAA Update / Sample Rate (in uS) (RW)
|
|
-- 0x7 A------- Force Trigger / Status (RW)
|
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 04/16/20 Revision block added
|
-- Seth Henry 12/14/20 Forked
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 73... |
Line 84... |
|
|
constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
|
constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
|
|
|
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
|
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic := '0';
|
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
|
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
|
signal Reg_Sel_q : std_logic_vector(2 downto 0);
|
signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
|
signal Wr_En_d : std_logic := '0';
|
signal Wr_En_d : std_logic := '0';
|
signal Wr_En_q : std_logic := '0';
|
signal Wr_En_q : std_logic := '0';
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En_d : std_logic := '0';
|
signal Rd_En_d : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
|
|
signal User_Trig : std_logic;
|
signal User_Trig : std_logic := '0';
|
|
|
signal Timer_Int : DATA_TYPE;
|
signal Timer_Int : DATA_TYPE := (others => '0');
|
signal Timer_Cnt : DATA_TYPE;
|
signal Timer_Cnt : DATA_TYPE := (others => '0');
|
signal Timer_Trig : std_logic;
|
signal Timer_Trig : std_logic := '0';
|
|
|
type ADC_STATES is ( IDLE, START, CLK_HIGH, CLK_HIGH2, CLK_LOW, CLK_LOW2, UPDATE );
|
type ADC_STATES is ( IDLE, START, CLK_HIGH, CLK_HIGH2, CLK_LOW, CLK_LOW2, UPDATE );
|
signal ad_state : ADC_STATES;
|
signal ad_state : ADC_STATES;
|
|
|
signal rx_buffer1 : std_logic_vector(16 downto 0);
|
signal rx_buffer1 : std_logic_vector(16 downto 0) := (others => '0');
|
signal rx_buffer2 : std_logic_vector(16 downto 0);
|
signal rx_buffer2 : std_logic_vector(16 downto 0) := (others => '0');
|
signal bit_cntr : std_logic_vector(4 downto 0);
|
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
|
constant BIT_COUNT : std_logic_vector(4 downto 0) :=
|
constant BIT_COUNT : std_logic_vector(4 downto 0) :=
|
conv_std_logic_vector(16,5);
|
conv_std_logic_vector(16,5);
|
|
|
signal ADC1_Data : std_logic_vector(13 downto 0);
|
signal ADC1_Data : std_logic_vector(13 downto 0) := (others => '0');
|
signal ADC2_Data : std_logic_vector(13 downto 0);
|
signal ADC2_Data : std_logic_vector(13 downto 0) := (others => '0');
|
signal ADC_Ready : std_logic;
|
signal ADC_Ready : std_logic := '0';
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
| Line 262... |
Line 274... |
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
