OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_mavg_8ch_16b_64d.vhd] - Diff between revs 323 and 324

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 323 Rev 324
Line 28... Line 28...
-- Register Map:
-- Register Map:
-- Offset  Bitfield Description                        Read/Write
-- Offset  Bitfield Description                        Read/Write
--   0x00  AAAAAAAA Raw Data (lower)                      (RW)
--   0x00  AAAAAAAA Raw Data (lower)                      (RW)
--   0x01  AAAAAAAA Raw Data (upper)                      (RW)
--   0x01  AAAAAAAA Raw Data (upper)                      (RW)
--   0x02  -----AAA Raw Channel Select                    (RW)
--   0x02  -----AAA Raw Channel Select                    (RW)
--   0x03  A------- Update Accum / Busy                   (RW)
--   0x03  BA------ Update Accum & Int Enable / Busy      (RW*)
--   0x04  AAAAAAAA Avg Data (lower)                      (RW)
--   0x04  AAAAAAAA Avg Data (lower)                      (RW)
--   0x05  AAAAAAAA Avg Data (upper)                      (RW)
--   0x05  AAAAAAAA Avg Data (upper)                      (RW)
--   0x06  -----AAA Avg Channel Select                    (RW)
--   0x06  -----AAA Avg Channel Select                    (RW)
--   0x07  A------- Flush Statistics  / Busy              (RW)
--   0x07  BA------ Flush Statistics & Int_Enable / Busy  (RW*)
 
--
 
-- Note: Writing bit A high will enable a CPU interrupt for the specified
 
--        operation. Writing a low will disable the interrupt. Bit B indicates
 
--        the operation status in either case.
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
Line 45... Line 49...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_mavg_8ch_16b_64d is
entity o8_mavg_8ch_16b_64d is
generic(
generic(
 
  Autoflush_On_Reset         : boolean := TRUE;
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Write_Qual                 : in  std_logic := '1';
  Write_Qual                 : in  std_logic := '1';
Line 85... Line 90...
  signal RAW_Valid           : std_logic := '0';
  signal RAW_Valid           : std_logic := '0';
 
 
  signal Flush_Valid         : std_logic := '0';
  signal Flush_Valid         : std_logic := '0';
  signal Flush_Busy          : std_logic := '0';
  signal Flush_Busy          : std_logic := '0';
 
 
  type AVG_CTL_STATES is (INIT, CLR_BUFF, IDLE, RD_LAST, ADV_PTR, CALC_NEXT,
  type AVG_CTL_STATES is (IDLE,
                          WR_NEW);
                          RD_LAST, ADV_PTR, CALC_NEXT, WR_NEW, AVG_DONE,
  signal AVG_Ctl             : AVG_CTL_STATES := INIT;
                          FLUSH_INIT, FLUSH_RAM, FLUSH_DONE);
 
  signal AVG_Ctl             : AVG_CTL_STATES := FLUSH_INIT;
 
 
  signal Avg_Busy            : std_logic := '0';
  signal Avg_Busy            : std_logic := '0';
 
 
  signal CH_Select           : std_logic_vector(2 downto 0) := (others => '0');
  signal CH_Select           : std_logic_vector(2 downto 0) := (others => '0');
  signal Data_New            : std_logic_vector(15 downto 0) := (others => '0');
  signal Data_New            : std_logic_vector(15 downto 0) := (others => '0');
Line 123... Line 129...
 
 
  signal AVG_Out             : std_logic_vector(15 downto 0);
  signal AVG_Out             : std_logic_vector(15 downto 0);
  alias AVG_Out_L            is AVG_Out(7 downto 0);
  alias AVG_Out_L            is AVG_Out(7 downto 0);
  alias AVG_Out_H            is AVG_Out(7 downto 0);
  alias AVG_Out_H            is AVG_Out(7 downto 0);
 
 
 
  signal AVG_Int_En          : std_logic := '0';
 
  signal Flush_Int_En        : std_logic := '0';
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Wr_En_d                    <= Addr_Match and Write_Qual and Open8_Bus.Wr_En;
  Wr_En_d                    <= Addr_Match and Write_Qual and Open8_Bus.Wr_En;
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
Line 146... Line 155...
      RAW_Channel            <= (others => '0');
      RAW_Channel            <= (others => '0');
 
 
      AVG_Out                <= (others => '0');
      AVG_Out                <= (others => '0');
      AVG_Channel            <= (others => '0');
      AVG_Channel            <= (others => '0');
 
 
 
      AVG_Int_En             <= '0';
 
      Flush_Int_En           <= '0';
 
 
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Reg_Sel_q              <= Reg_Sel_d;
      Reg_Sel_q              <= Reg_Sel_d;
      Wr_En_q                <= Wr_En_d;
      Wr_En_q                <= Wr_En_d;
      Wr_Data_q              <= Wr_Data_d;
      Wr_Data_q              <= Wr_Data_d;
 
 
 
      Flush_Valid            <= '0';
      RAW_Valid              <= '0';
      RAW_Valid              <= '0';
 
 
      if( Wr_En_q = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Sel_q )is
        case( Reg_Sel_q )is
          when "000" =>
          when "000" =>
Line 166... Line 178...
 
 
          when "010" =>
          when "010" =>
            RAW_Channel      <= Wr_Data_q(2 downto 0);
            RAW_Channel      <= Wr_Data_q(2 downto 0);
 
 
          when "011" =>
          when "011" =>
            RAW_Valid        <= not Avg_Busy;
            AVG_Int_En       <= Wr_Data_q(6);
 
            RAW_Valid        <= not (Flush_Busy or Avg_Busy);
 
 
          when "110" =>
          when "110" =>
            AVG_Channel      <= Wr_Data_q(2 downto 0);
            AVG_Channel      <= Wr_Data_q(2 downto 0);
 
 
          when "111" =>
          when "111" =>
            Flush_Valid      <= not Flush_Busy;
            Flush_Int_En     <= Wr_Data_q(6);
 
            Flush_Valid      <= not (Flush_Busy or Avg_Busy);
 
 
          when others =>
          when others =>
            null;
            null;
 
 
        end case;
        end case;
Line 197... Line 211...
 
 
          when "010" =>
          when "010" =>
            Rd_Data          <= "00000" & RAW_Channel;
            Rd_Data          <= "00000" & RAW_Channel;
 
 
          when "011" =>
          when "011" =>
            Rd_Data          <= Avg_Busy & "0000000";
            Rd_Data          <= Avg_Busy & AVG_Int_En & "000000";
 
 
          when "100" =>
          when "100" =>
            Rd_Data          <= AVG_Out_L;
            Rd_Data          <= AVG_Out_L;
 
 
          when "101" =>
          when "101" =>
Line 209... Line 223...
 
 
          when "110" =>
          when "110" =>
            Rd_Data          <= "00000" & AVG_Channel;
            Rd_Data          <= "00000" & AVG_Channel;
 
 
          when "111" =>
          when "111" =>
            Rd_Data          <= Flush_Busy & "0000000";
            Rd_Data          <= Flush_Busy & Flush_Int_En & "000000";
 
 
          when others =>
          when others =>
            null;
            null;
 
 
        end case;
        end case;
Line 224... Line 238...
 
 
  MAVG_Control_proc: process( Clock, Reset )
  MAVG_Control_proc: process( Clock, Reset )
    variable i : integer := 0;
    variable i : integer := 0;
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      AVG_Ctl                <= INIT;
      AVG_Ctl                <= IDLE;
 
      if( Autoflush_On_Reset )then
 
        AVG_Ctl              <= FLUSH_INIT;
 
      end if;
 
 
      CH_Select              <= (others => '0');
      CH_Select              <= (others => '0');
      Data_New               <= (others => '0');
      Data_New               <= (others => '0');
 
 
      Flush_Busy             <= '0';
      Flush_Busy             <= '0';
Line 252... Line 269...
      Interrupt              <= '0';
      Interrupt              <= '0';
 
 
      RAM_Wr_En              <= '0';
      RAM_Wr_En              <= '0';
 
 
      Flush_Busy             <= '0';
      Flush_Busy             <= '0';
      Avg_Busy               <= '1';
      Avg_Busy               <= '0';
 
 
      i                      := conv_integer(unsigned(CH_Select));
      i                      := conv_integer(unsigned(CH_Select));
 
 
      case( AVG_Ctl )is
      case( AVG_Ctl )is
        when INIT =>
 
           Flush_Busy        <= '1';
 
          RAM_Wr_Addr        <= (others => '0');
 
          RAM_Wr_Data        <= (others => '0');
 
          AVG_Ctl            <= CLR_BUFF;
 
 
 
        when CLR_BUFF =>
 
          Flush_Busy         <= '1';
 
          RAM_Wr_Addr        <= RAM_Wr_Addr + 1;
 
          RAM_Wr_En          <= '1';
 
          if( and_reduce(RAM_Wr_Addr) = '1' )then
 
            AVG_Ctl          <= IDLE;
 
          end if;
 
 
 
        when IDLE =>
        when IDLE =>
          Avg_Busy           <= '0';
 
          if( Flush_Valid = '1' )then
          if( Flush_Valid = '1' )then
            AVG_Ctl          <= INIT;
            AVG_Ctl          <= FLUSH_INIT;
          elsif( RAW_Valid = '1' )then
          elsif( RAW_Valid = '1' )then
            Data_New         <= RAW_Data;
            Data_New         <= RAW_Data;
            CH_Select        <= RAW_Channel;
            CH_Select        <= RAW_Channel;
            AVG_Ctl          <= RD_LAST;
            AVG_Ctl          <= RD_LAST;
          end if;
          end if;
 
 
 
        -- Data Average Update States
        when RD_LAST =>
        when RD_LAST =>
 
          Avg_Busy           <= '1';
          RAM_Rd_Chan        <= CH_Select;
          RAM_Rd_Chan        <= CH_Select;
          RAM_Rd_Ptr         <= SPN_Pointers(i);
          RAM_Rd_Ptr         <= SPN_Pointers(i);
          AVG_Ctl            <= ADV_PTR;
          AVG_Ctl            <= ADV_PTR;
 
 
        when ADV_PTR =>
        when ADV_PTR =>
 
          Avg_Busy           <= '1';
          SP0_Pointers(i)    <= SP0_Pointers(i) + 1;
          SP0_Pointers(i)    <= SP0_Pointers(i) + 1;
          AVG_Ctl            <= CALC_NEXT;
          AVG_Ctl            <= CALC_NEXT;
 
 
        when CALC_NEXT =>
        when CALC_NEXT =>
 
          Avg_Busy           <= '1';
          Accumulators(i)    <= Accumulators(i) +
          Accumulators(i)    <= Accumulators(i) +
                                unsigned( Data_New ) -
                                unsigned( Data_New ) -
                                unsigned( Data_Old );
                                unsigned( Data_Old );
          AVG_Ctl            <= WR_NEW;
          AVG_Ctl            <= WR_NEW;
 
 
        when WR_NEW =>
        when WR_NEW =>
 
          Avg_Busy           <= '1';
          RAM_Wr_Chan        <= CH_Select;
          RAM_Wr_Chan        <= CH_Select;
          RAM_Wr_Ptr         <= SP0_Pointers(i);
          RAM_Wr_Ptr         <= SP0_Pointers(i);
          RAM_Wr_Data        <= Data_New;
          RAM_Wr_Data        <= Data_New;
          RAM_Wr_En          <= '1';
          RAM_Wr_En          <= '1';
          SPN_Pointers(i)    <= SP0_Pointers(i) + 1;
          SPN_Pointers(i)    <= SP0_Pointers(i) + 1;
          Interrupt          <= '1';
          AVG_Ctl            <= AVG_DONE;
 
 
 
        when AVG_DONE =>
 
          Interrupt          <= AVG_Int_En;
 
          AVG_Ctl            <= IDLE;
 
 
 
        -- Buffer Flush States
 
        when FLUSH_INIT =>
 
          Flush_Busy         <= '1';
 
          RAM_Wr_Addr        <= (others => '0');
 
          RAM_Wr_Data        <= (others => '0');
 
          AVG_Ctl            <= FLUSH_RAM;
 
 
 
        when FLUSH_RAM =>
 
          Flush_Busy         <= '1';
 
          RAM_Wr_Addr        <= RAM_Wr_Addr + 1;
 
          RAM_Wr_En          <= '1';
 
          if( and_reduce(RAM_Wr_Addr) = '1' )then
 
            AVG_Ctl          <= FLUSH_DONE;
 
          end if;
 
 
 
        when FLUSH_DONE =>
 
          Interrupt          <= Flush_Int_En;
          AVG_Ctl            <= IDLE;
          AVG_Ctl            <= IDLE;
 
 
        when others =>
        when others =>
          null;
          null;
      end case;
      end case;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.