| Line 28... |
Line 28... |
-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Raw Data (lower) (RW)
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-- 0x00 AAAAAAAA Raw Data (lower) (RW)
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-- 0x01 AAAAAAAA Raw Data (upper) (RW)
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-- 0x01 AAAAAAAA Raw Data (upper) (RW)
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-- 0x02 -----AAA Raw Channel Select (RW)
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-- 0x02 -----AAA Raw Channel Select (RW)
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-- 0x03 A------- Update Accum / Busy (RW)
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-- 0x03 BA------ Update Accum & Int Enable / Busy (RW*)
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-- 0x04 AAAAAAAA Avg Data (lower) (RW)
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-- 0x04 AAAAAAAA Avg Data (lower) (RW)
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-- 0x05 AAAAAAAA Avg Data (upper) (RW)
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-- 0x05 AAAAAAAA Avg Data (upper) (RW)
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-- 0x06 -----AAA Avg Channel Select (RW)
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-- 0x06 -----AAA Avg Channel Select (RW)
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-- 0x07 A------- Flush Statistics / Busy (RW)
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-- 0x07 BA------ Flush Statistics & Int_Enable / Busy (RW*)
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--
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-- Note: Writing bit A high will enable a CPU interrupt for the specified
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-- operation. Writing a low will disable the interrupt. Bit B indicates
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-- the operation status in either case.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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| Line 45... |
Line 49... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_mavg_8ch_16b_64d is
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entity o8_mavg_8ch_16b_64d is
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generic(
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generic(
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Autoflush_On_Reset : boolean := TRUE;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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| Line 85... |
Line 90... |
signal RAW_Valid : std_logic := '0';
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signal RAW_Valid : std_logic := '0';
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signal Flush_Valid : std_logic := '0';
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signal Flush_Valid : std_logic := '0';
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signal Flush_Busy : std_logic := '0';
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signal Flush_Busy : std_logic := '0';
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type AVG_CTL_STATES is (INIT, CLR_BUFF, IDLE, RD_LAST, ADV_PTR, CALC_NEXT,
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type AVG_CTL_STATES is (IDLE,
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WR_NEW);
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RD_LAST, ADV_PTR, CALC_NEXT, WR_NEW, AVG_DONE,
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signal AVG_Ctl : AVG_CTL_STATES := INIT;
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FLUSH_INIT, FLUSH_RAM, FLUSH_DONE);
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signal AVG_Ctl : AVG_CTL_STATES := FLUSH_INIT;
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signal Avg_Busy : std_logic := '0';
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signal Avg_Busy : std_logic := '0';
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signal CH_Select : std_logic_vector(2 downto 0) := (others => '0');
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signal CH_Select : std_logic_vector(2 downto 0) := (others => '0');
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signal Data_New : std_logic_vector(15 downto 0) := (others => '0');
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signal Data_New : std_logic_vector(15 downto 0) := (others => '0');
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| Line 123... |
Line 129... |
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signal AVG_Out : std_logic_vector(15 downto 0);
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signal AVG_Out : std_logic_vector(15 downto 0);
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alias AVG_Out_L is AVG_Out(7 downto 0);
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alias AVG_Out_L is AVG_Out(7 downto 0);
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alias AVG_Out_H is AVG_Out(7 downto 0);
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alias AVG_Out_H is AVG_Out(7 downto 0);
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signal AVG_Int_En : std_logic := '0';
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signal Flush_Int_En : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Write_Qual and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Write_Qual and Open8_Bus.Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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| Line 146... |
Line 155... |
RAW_Channel <= (others => '0');
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RAW_Channel <= (others => '0');
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AVG_Out <= (others => '0');
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AVG_Out <= (others => '0');
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AVG_Channel <= (others => '0');
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AVG_Channel <= (others => '0');
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AVG_Int_En <= '0';
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Flush_Int_En <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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Flush_Valid <= '0';
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RAW_Valid <= '0';
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RAW_Valid <= '0';
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if( Wr_En_q = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "000" =>
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when "000" =>
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| Line 166... |
Line 178... |
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when "010" =>
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when "010" =>
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RAW_Channel <= Wr_Data_q(2 downto 0);
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RAW_Channel <= Wr_Data_q(2 downto 0);
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when "011" =>
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when "011" =>
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RAW_Valid <= not Avg_Busy;
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AVG_Int_En <= Wr_Data_q(6);
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RAW_Valid <= not (Flush_Busy or Avg_Busy);
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when "110" =>
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when "110" =>
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AVG_Channel <= Wr_Data_q(2 downto 0);
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AVG_Channel <= Wr_Data_q(2 downto 0);
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when "111" =>
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when "111" =>
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Flush_Valid <= not Flush_Busy;
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Flush_Int_En <= Wr_Data_q(6);
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Flush_Valid <= not (Flush_Busy or Avg_Busy);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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| Line 197... |
Line 211... |
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when "010" =>
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when "010" =>
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Rd_Data <= "00000" & RAW_Channel;
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Rd_Data <= "00000" & RAW_Channel;
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when "011" =>
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when "011" =>
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Rd_Data <= Avg_Busy & "0000000";
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Rd_Data <= Avg_Busy & AVG_Int_En & "000000";
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when "100" =>
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when "100" =>
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Rd_Data <= AVG_Out_L;
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Rd_Data <= AVG_Out_L;
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when "101" =>
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when "101" =>
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| Line 209... |
Line 223... |
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when "110" =>
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when "110" =>
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Rd_Data <= "00000" & AVG_Channel;
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Rd_Data <= "00000" & AVG_Channel;
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when "111" =>
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when "111" =>
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Rd_Data <= Flush_Busy & "0000000";
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Rd_Data <= Flush_Busy & Flush_Int_En & "000000";
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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| Line 224... |
Line 238... |
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MAVG_Control_proc: process( Clock, Reset )
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MAVG_Control_proc: process( Clock, Reset )
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variable i : integer := 0;
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variable i : integer := 0;
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begin
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begin
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if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
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AVG_Ctl <= INIT;
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AVG_Ctl <= IDLE;
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if( Autoflush_On_Reset )then
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AVG_Ctl <= FLUSH_INIT;
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end if;
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CH_Select <= (others => '0');
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CH_Select <= (others => '0');
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Data_New <= (others => '0');
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Data_New <= (others => '0');
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Flush_Busy <= '0';
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Flush_Busy <= '0';
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| Line 252... |
Line 269... |
Interrupt <= '0';
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Interrupt <= '0';
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RAM_Wr_En <= '0';
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RAM_Wr_En <= '0';
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Flush_Busy <= '0';
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Flush_Busy <= '0';
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Avg_Busy <= '1';
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Avg_Busy <= '0';
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i := conv_integer(unsigned(CH_Select));
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i := conv_integer(unsigned(CH_Select));
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case( AVG_Ctl )is
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case( AVG_Ctl )is
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when INIT =>
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Flush_Busy <= '1';
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RAM_Wr_Addr <= (others => '0');
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RAM_Wr_Data <= (others => '0');
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AVG_Ctl <= CLR_BUFF;
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when CLR_BUFF =>
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Flush_Busy <= '1';
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RAM_Wr_Addr <= RAM_Wr_Addr + 1;
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RAM_Wr_En <= '1';
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if( and_reduce(RAM_Wr_Addr) = '1' )then
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AVG_Ctl <= IDLE;
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end if;
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when IDLE =>
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when IDLE =>
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Avg_Busy <= '0';
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if( Flush_Valid = '1' )then
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if( Flush_Valid = '1' )then
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AVG_Ctl <= INIT;
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AVG_Ctl <= FLUSH_INIT;
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elsif( RAW_Valid = '1' )then
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elsif( RAW_Valid = '1' )then
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Data_New <= RAW_Data;
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Data_New <= RAW_Data;
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CH_Select <= RAW_Channel;
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CH_Select <= RAW_Channel;
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AVG_Ctl <= RD_LAST;
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AVG_Ctl <= RD_LAST;
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end if;
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end if;
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-- Data Average Update States
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when RD_LAST =>
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when RD_LAST =>
|
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Avg_Busy <= '1';
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RAM_Rd_Chan <= CH_Select;
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RAM_Rd_Chan <= CH_Select;
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RAM_Rd_Ptr <= SPN_Pointers(i);
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RAM_Rd_Ptr <= SPN_Pointers(i);
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AVG_Ctl <= ADV_PTR;
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AVG_Ctl <= ADV_PTR;
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when ADV_PTR =>
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when ADV_PTR =>
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Avg_Busy <= '1';
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SP0_Pointers(i) <= SP0_Pointers(i) + 1;
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SP0_Pointers(i) <= SP0_Pointers(i) + 1;
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AVG_Ctl <= CALC_NEXT;
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AVG_Ctl <= CALC_NEXT;
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when CALC_NEXT =>
|
when CALC_NEXT =>
|
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Avg_Busy <= '1';
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Accumulators(i) <= Accumulators(i) +
|
Accumulators(i) <= Accumulators(i) +
|
unsigned( Data_New ) -
|
unsigned( Data_New ) -
|
unsigned( Data_Old );
|
unsigned( Data_Old );
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AVG_Ctl <= WR_NEW;
|
AVG_Ctl <= WR_NEW;
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|
when WR_NEW =>
|
when WR_NEW =>
|
|
Avg_Busy <= '1';
|
RAM_Wr_Chan <= CH_Select;
|
RAM_Wr_Chan <= CH_Select;
|
RAM_Wr_Ptr <= SP0_Pointers(i);
|
RAM_Wr_Ptr <= SP0_Pointers(i);
|
RAM_Wr_Data <= Data_New;
|
RAM_Wr_Data <= Data_New;
|
RAM_Wr_En <= '1';
|
RAM_Wr_En <= '1';
|
SPN_Pointers(i) <= SP0_Pointers(i) + 1;
|
SPN_Pointers(i) <= SP0_Pointers(i) + 1;
|
Interrupt <= '1';
|
AVG_Ctl <= AVG_DONE;
|
|
|
|
when AVG_DONE =>
|
|
Interrupt <= AVG_Int_En;
|
|
AVG_Ctl <= IDLE;
|
|
|
|
-- Buffer Flush States
|
|
when FLUSH_INIT =>
|
|
Flush_Busy <= '1';
|
|
RAM_Wr_Addr <= (others => '0');
|
|
RAM_Wr_Data <= (others => '0');
|
|
AVG_Ctl <= FLUSH_RAM;
|
|
|
|
when FLUSH_RAM =>
|
|
Flush_Busy <= '1';
|
|
RAM_Wr_Addr <= RAM_Wr_Addr + 1;
|
|
RAM_Wr_En <= '1';
|
|
if( and_reduce(RAM_Wr_Addr) = '1' )then
|
|
AVG_Ctl <= FLUSH_DONE;
|
|
end if;
|
|
|
|
when FLUSH_DONE =>
|
|
Interrupt <= Flush_Int_En;
|
AVG_Ctl <= IDLE;
|
AVG_Ctl <= IDLE;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
