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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 3)
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constant User_Addr : std_logic_vector(15 downto 3)
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:= Address(15 downto 3);
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:= Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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type ACCUM_ARRAY is array (0 to 7) of unsigned(21 downto 0);
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type ACCUM_ARRAY is array (0 to 7) of unsigned(21 downto 0);
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signal Accumulators : ACCUM_ARRAY;
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signal Accumulators : ACCUM_ARRAY;
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signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal AVG_Out : std_logic_vector(15 downto 0);
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signal AVG_Out : std_logic_vector(15 downto 0) := (others => '0');
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alias AVG_Out_L is AVG_Out(7 downto 0);
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alias AVG_Out_L is AVG_Out(7 downto 0);
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alias AVG_Out_H is AVG_Out(7 downto 0);
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alias AVG_Out_H is AVG_Out(7 downto 0);
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signal AVG_Int_En : std_logic := '0';
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signal AVG_Int_En : std_logic := '0';
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signal Flush_Int_En : std_logic := '0';
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signal Flush_Int_En : std_logic := '0';
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