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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_max7221.vhd] - Diff between revs 213 and 217
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architecture behave of o8_max7221 is
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architecture behave of o8_max7221 is
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signal FIFO_Reset : std_logic;
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signal FIFO_Reset : std_logic;
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constant User_Addr : std_logic_vector(15 downto 4) := Address(15 downto 4);
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constant User_Addr : std_logic_vector(15 downto 4) :=
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Address(15 downto 4);
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alias Comp_Addr is Bus_Address(15 downto 4);
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alias Comp_Addr is Bus_Address(15 downto 4);
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signal FIFO_Wr_En : std_logic;
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signal FIFO_Wr_En : std_logic;
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signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
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signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
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