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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_max7221.vhd] - Diff between revs 217 and 223

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Rev 217 Rev 223
Line 48... Line 48... 
);
 
);
 
port(
 
port(
 
  Clock                      : in  std_logic;
 
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  --
 
  --
 
  Bus_Address                : in  ADDRESS_TYPE;
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Wr_Enable                  : in  std_logic;
 
 
 
  Wr_Data                    : in  DATA_TYPE;
 
 
 
  --
 
  --
 
  Mx_Data                    : out std_logic;
 
  Mx_Data                    : out std_logic;
 
  Mx_Clock                   : out std_logic;
 
  Mx_Clock                   : out std_logic;
 
  MX_LDCSn                   : out std_logic
 
  MX_LDCSn                   : out std_logic
 
);
 
);
Line 64... Line 62... 
 
 
 
 
  signal FIFO_Reset          : std_logic;
 
  signal FIFO_Reset          : std_logic;
 
 
 
 
 
  constant User_Addr         : std_logic_vector(15 downto 4) :=
 
  constant User_Addr         : std_logic_vector(15 downto 4) :=
 
                                 Address(15 downto 4);
 
                                 Address(15 downto 4);
 
  alias  Comp_Addr           is Bus_Address(15 downto 4);
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 4);
 
 
 
 
 
  signal FIFO_Wr_En          : std_logic;
 
  signal FIFO_Wr_En          : std_logic;
 
  signal FIFO_Wr_Data        : std_logic_vector(11 downto 0);
 
  signal FIFO_Wr_Data        : std_logic_vector(11 downto 0);
 
 
 
 
 
  signal FIFO_Rd_En          : std_logic;
 
  signal FIFO_Rd_En          : std_logic;
Line 95... Line 93... 
  signal bit_cntr            : std_logic_vector(3 downto 0);
 
  signal bit_cntr            : std_logic_vector(3 downto 0);
 
  signal tx_buffer           : std_logic_vector(15 downto 0);
 
  signal tx_buffer           : std_logic_vector(15 downto 0);
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  FIFO_Wr_En                 <= Wr_Enable when Comp_Addr = User_Addr else '0';
 
  FIFO_Wr_En                 <= Open8_Bus.Wr_En when Comp_Addr = User_Addr else
 
  FIFO_Wr_Data               <= Bus_Address(3 downto 0) & Wr_Data;
 
                                '0';
 
 
 
 
 
 
 
  FIFO_Wr_Data               <= Open8_Bus.Address(3 downto 0) &
 
 
 
                                Open8_Bus.Wr_Data;
 
 
 
 
 
  FIFO_Reset                 <= Reset when Reset_Level = '1' else (not Reset);
 
  FIFO_Reset                 <= Reset when Reset_Level = '1' else (not Reset);
 
 
 
 
 
  U_FIFO : entity work.o8_max7221_fifo
 
  U_FIFO : entity work.o8_max7221_fifo
 
  port map(
 
  port map(
 
    aclr                     => FIFO_Reset,
 
    aclr                     => FIFO_Reset,

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