| Line 27... |
Line 27... |
--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/20 Design Start
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-- Seth Henry 01/22/20 Design Start
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 39... |
Line 40... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_max7221 is
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entity o8_max7221 is
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generic(
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generic(
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Bit_Rate : real := 5000000.0;
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Bitclock_Frequency : real := 5000000.0;
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Sys_Freq : real;
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Clock_Frequency : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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--
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--
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Mx_Data : out std_logic;
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Mx_Data : out std_logic;
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Mx_Clock : out std_logic;
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Mx_Clock : out std_logic;
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MX_LDCSn : out std_logic
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MX_LDCSn : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_max7221 is
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architecture behave of o8_max7221 is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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signal FIFO_Reset : std_logic;
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signal FIFO_Reset : std_logic;
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constant User_Addr : std_logic_vector(15 downto 4) :=
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constant User_Addr : std_logic_vector(15 downto 4) :=
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Address(15 downto 4);
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Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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| Line 77... |
Line 77... |
signal TX_Ctrl : TX_CTRL_STATES;
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signal TX_Ctrl : TX_CTRL_STATES;
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signal TX_En : std_logic;
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signal TX_En : std_logic;
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signal TX_Idle : std_logic;
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signal TX_Idle : std_logic;
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constant BAUD_DLY_VAL : integer := integer((Sys_Freq / Bit_Rate)/ 2.0);
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constant BAUD_DLY_RATIO : real := (Clock_Frequency / Bitclock_Frequency);
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constant BAUD_DLY_VAL : integer := integer(BAUD_DLY_RATIO * 0.5);
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constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
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constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
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constant BAUD_DLY : std_logic_vector :=
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constant BAUD_DLY : std_logic_vector :=
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conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
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conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
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signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
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signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
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