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Line 28... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/20 Design Start
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-- Seth Henry 01/22/20 Design Start
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 46... |
Line 47... |
Clock_Frequency : real;
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Clock_Frequency : real;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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--
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--
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Mx_Data : out std_logic;
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Mx_Data : out std_logic;
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Mx_Clock : out std_logic;
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Mx_Clock : out std_logic;
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MX_LDCSn : out std_logic
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MX_LDCSn : out std_logic
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);
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);
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signal FIFO_Reset : std_logic;
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signal FIFO_Reset : std_logic;
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constant User_Addr : std_logic_vector(15 downto 4) :=
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constant User_Addr : std_logic_vector(15 downto 4) :=
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Address(15 downto 4);
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Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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alias Comp_Addr is Open8_Bus.Address(15 downto 4);
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signal Addr_Match : std_logic := '0';
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signal FIFO_Wr_En : std_logic;
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signal FIFO_Wr_En : std_logic := '0';
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signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
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signal FIFO_Wr_Data : std_logic_vector(11 downto 0) :=
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(others => '0');
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signal FIFO_Rd_En : std_logic;
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signal FIFO_Empty : std_logic;
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signal FIFO_Rd_En : std_logic := '0';
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signal FIFO_Rd_Data : std_logic_vector(11 downto 0);
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signal FIFO_Empty : std_logic := '0';
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signal FIFO_Rd_Data : std_logic_vector(11 downto 0) :=
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(others => '0');
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type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
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type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
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signal TX_Ctrl : TX_CTRL_STATES;
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signal TX_Ctrl : TX_CTRL_STATES := IDLE;
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signal TX_En : std_logic;
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signal TX_En : std_logic := '0';
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signal TX_Idle : std_logic;
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signal TX_Idle : std_logic := '0';
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constant BAUD_DLY_RATIO : real := (Clock_Frequency / Bitclock_Frequency);
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constant BAUD_DLY_RATIO : real := (Clock_Frequency / Bitclock_Frequency);
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constant BAUD_DLY_VAL : integer := integer(BAUD_DLY_RATIO * 0.5);
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constant BAUD_DLY_VAL : integer := integer(BAUD_DLY_RATIO * 0.5);
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constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
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constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
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constant BAUD_DLY : std_logic_vector :=
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constant BAUD_DLY : std_logic_vector :=
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conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
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conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
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signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
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signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
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:= (others => '0');
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:= (others => '0');
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signal Baud_Tick : std_logic;
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signal Baud_Tick : std_logic := '0';
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type IO_STATES is ( IDLE, SYNC_CLK, SCLK_L, SCLK_H, ADV_BIT, DONE );
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type IO_STATES is ( IDLE, SYNC_CLK, SCLK_L, SCLK_H, ADV_BIT, DONE );
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signal io_state : IO_STATES;
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signal io_state : IO_STATES := IDLE;
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signal bit_cntr : std_logic_vector(3 downto 0);
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signal bit_cntr : std_logic_vector(3 downto 0) := (others => '0');
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signal tx_buffer : std_logic_vector(15 downto 0);
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signal tx_buffer : std_logic_vector(15 downto 0) :=
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(others => '0');
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begin
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begin
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FIFO_Wr_En <= Open8_Bus.Wr_En when Comp_Addr = User_Addr else
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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'0';
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FIFO_Wr_En <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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FIFO_Wr_Data <= Open8_Bus.Address(3 downto 0) &
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FIFO_Wr_Data <= Open8_Bus.Address(3 downto 0) &
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Open8_Bus.Wr_Data;
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Open8_Bus.Wr_Data;
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FIFO_Reset <= Reset when Reset_Level = '1' else (not Reset);
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FIFO_Reset <= Reset when Reset_Level = '1' else (not Reset);
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