| Line 57... |
Line 57... |
port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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uSec_Tick : in std_logic;
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uSec_Tick : in std_logic;
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--
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--
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PWM_Out : out std_logic;
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Open8_Bus : in OPEN8_BUS_TYPE;
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-- Bus interface
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic;
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--
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PWM_Out : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_pwm16 is
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architecture behave of o8_pwm16 is
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constant User_Addr : std_logic_vector(15 downto 3) :=
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constant User_Addr : std_logic_vector(15 downto 3) :=
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Address(15 downto 3);
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Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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|
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alias Reg_Addr is Bus_Address(2 downto 0);
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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| Line 118... |
Line 115... |
Period_Ctr <= (others => '0');
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Period_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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PWM_Out <= '0';
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PWM_Out <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Addr_q <= Reg_Addr;
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Reg_Addr_q <= Reg_Addr;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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PWM_Period_l <= Wr_Data_q;
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PWM_Period_l <= Wr_Data_q;
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| Line 138... |
Line 135... |
when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= PWM_Period_l;
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Rd_Data <= PWM_Period_l;
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when "001" =>
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when "001" =>
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