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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_pwm16.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 38... Line 38...
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      04/25/18 Design Start
-- Seth Henry      04/25/18 Design Start
-- Seth Henry      04/10/20 Code cleanup and comments
-- Seth Henry      04/10/20 Code cleanup and comments
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_misc.all;
  use ieee.std_logic_misc.all;
Line 49... Line 50...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_pwm16 is
entity o8_pwm16 is
generic(
generic(
  Reset_Level                : std_logic;
 
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  uSec_Tick                  : in  std_logic;
 
  --
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic;
  Interrupt                  : out std_logic;
  --
  --
  PWM_Out                    : out std_logic
  PWM_Out                    : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_pwm16 is
architecture behave of o8_pwm16 is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : std_logic_vector(15 downto 3) :=
  constant User_Addr         : std_logic_vector(15 downto 3) :=
                                Address(15 downto 3);
                                Address(15 downto 3);
 
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';

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