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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_pwm16.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 54... Line 54...
generic(
generic(
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic;
  Interrupt                  : out std_logic;
  --
  --
  PWM_Out                    : out std_logic
  PWM_Out                    : out std_logic
);
);
Line 73... Line 74...
                                Address(15 downto 3);
                                Address(15 downto 3);
 
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
 
 
  alias  Reg_Addr            is Open8_Bus.Address(2 downto 0);
  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
  signal Reg_Addr_q          : std_logic_vector(2 downto 0) := (others => '0');
  signal Reg_Sel_q           : std_logic_vector(2 downto 0) := (others => '0');
 
  signal Wr_En_d             : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Rd_En               : std_logic := '0';
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal PWM_Enable          : std_logic := '0';
  signal PWM_Enable          : std_logic := '0';
  signal PWM_Period          : std_logic_vector(15 downto 0) := (others => '0');
  signal PWM_Period          : std_logic_vector(15 downto 0) := (others => '0');
  alias  PWM_Period_l        is PWM_Period(7 downto 0);
  alias  PWM_Period_l        is PWM_Period(7 downto 0);
  alias  PWM_Period_u        is PWM_Period(15 downto 8);
  alias  PWM_Period_u        is PWM_Period(15 downto 8);
Line 95... Line 98...
  signal Width_Ctr           : std_logic_vector(15 downto 0) := (others => '0');
  signal Width_Ctr           : std_logic_vector(15 downto 0) := (others => '0');
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  PWM_proc: process( Clock, Reset )
  PWM_proc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Wr_Data_q              <= (others => '0');
      Reg_Sel_q              <= "000";
      Reg_Addr_q             <= (others => '0');
      Wr_En_q                <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= x"00";
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      Interrupt              <= '0';
      Interrupt              <= '0';
 
 
      PWM_Enable             <= '0';
      PWM_Enable             <= '0';
      PWM_Period             <= (others => '0');
      PWM_Period             <= (others => '0');
      PWM_Width              <= (others => '0');
      PWM_Width              <= (others => '0');
 
 
      Period_Ctr             <= (others => '0');
      Period_Ctr             <= (others => '0');
      Width_Ctr              <= (others => '0');
      Width_Ctr              <= (others => '0');
      PWM_Out                <= '0';
      PWM_Out                <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Reg_Addr_q             <= Reg_Addr;
      Reg_Sel_q              <= Reg_Sel_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
 
 
 
      if( Wr_En = '1' )then
      Wr_En_q                <= Wr_En_d;
        case( Reg_Addr_q )is
      Wr_Data_q              <= Wr_Data_d;
 
      if( Wr_En_q = '1' )then
 
        case( Reg_Sel_q )is
          when "000" =>
          when "000" =>
            PWM_Period_l     <= Wr_Data_q;
            PWM_Period_l     <= Wr_Data_q;
          when "001" =>
          when "001" =>
            PWM_Period_u     <= Wr_Data_q;
            PWM_Period_u     <= Wr_Data_q;
          when "010" =>
          when "010" =>
Line 134... Line 140...
            PWM_Enable       <= Wr_Data_q(7);
            PWM_Enable       <= Wr_Data_q(7);
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
      Rd_Data                <= (others => '0');
      Rd_En_q                <= Rd_En_d;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
      if( Rd_En_q = '1' )then
        case( Reg_Addr_q )is
        case( Reg_Sel_q )is
          when "000" =>
          when "000" =>
            Rd_Data          <= PWM_Period_l;
            Rd_Data          <= PWM_Period_l;
          when "001" =>
          when "001" =>
            Rd_Data          <= PWM_Period_u;
            Rd_Data          <= PWM_Period_u;
          when "010" =>
          when "010" =>

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