| Line 54... |
Line 54... |
generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
|
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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PWM_Out : out std_logic
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PWM_Out : out std_logic
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);
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);
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| Line 73... |
Line 74... |
Address(15 downto 3);
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Address(15 downto 3);
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|
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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|
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Wr_En_d : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
|
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signal Rd_En_q : std_logic := '0';
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|
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signal PWM_Enable : std_logic := '0';
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signal PWM_Enable : std_logic := '0';
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signal PWM_Period : std_logic_vector(15 downto 0) := (others => '0');
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signal PWM_Period : std_logic_vector(15 downto 0) := (others => '0');
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alias PWM_Period_l is PWM_Period(7 downto 0);
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alias PWM_Period_l is PWM_Period(7 downto 0);
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alias PWM_Period_u is PWM_Period(15 downto 8);
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alias PWM_Period_u is PWM_Period(15 downto 8);
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| Line 95... |
Line 98... |
signal Width_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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signal Width_Ctr : std_logic_vector(15 downto 0) := (others => '0');
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|
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begin
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begin
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|
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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|
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PWM_proc: process( Clock, Reset )
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PWM_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
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Wr_Data_q <= (others => '0');
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Reg_Sel_q <= "000";
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Reg_Addr_q <= (others => '0');
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Wr_En_q <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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|
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Interrupt <= '0';
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Interrupt <= '0';
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|
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PWM_Enable <= '0';
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PWM_Enable <= '0';
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PWM_Period <= (others => '0');
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PWM_Period <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Width <= (others => '0');
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|
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Period_Ctr <= (others => '0');
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Period_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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PWM_Out <= '0';
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PWM_Out <= '0';
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elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
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Reg_Addr_q <= Reg_Addr;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
|
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
|
|
|
if( Wr_En = '1' )then
|
Wr_En_q <= Wr_En_d;
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case( Reg_Addr_q )is
|
Wr_Data_q <= Wr_Data_d;
|
|
if( Wr_En_q = '1' )then
|
|
case( Reg_Sel_q )is
|
when "000" =>
|
when "000" =>
|
PWM_Period_l <= Wr_Data_q;
|
PWM_Period_l <= Wr_Data_q;
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when "001" =>
|
when "001" =>
|
PWM_Period_u <= Wr_Data_q;
|
PWM_Period_u <= Wr_Data_q;
|
when "010" =>
|
when "010" =>
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| Line 134... |
Line 140... |
PWM_Enable <= Wr_Data_q(7);
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PWM_Enable <= Wr_Data_q(7);
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when others => null;
|
when others => null;
|
end case;
|
end case;
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end if;
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end if;
|
|
|
Rd_Data <= (others => '0');
|
Rd_En_q <= Rd_En_d;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
|
if( Rd_En_q = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Sel_q )is
|
when "000" =>
|
when "000" =>
|
Rd_Data <= PWM_Period_l;
|
Rd_Data <= PWM_Period_l;
|
when "001" =>
|
when "001" =>
|
Rd_Data <= PWM_Period_u;
|
Rd_Data <= PWM_Period_u;
|
when "010" =>
|
when "010" =>
|
