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Line 58... |
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constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
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constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Sample : DATA_TYPE := x"00";
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signal Sample : DATA_TYPE := x"00";
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signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
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signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
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signal RAM_Data : DATA_TYPE := x"00";
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signal RAM_Data : DATA_TYPE := x"00";
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signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
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signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
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signal Average : DATA_TYPE := x"00";
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signal Average : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Average;
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Rd_Data <= Average;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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