| Line 54... |
Line 54... |
constant User_Addr : std_logic_vector(15 downto 10)
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constant User_Addr : std_logic_vector(15 downto 10)
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:= Address(15 downto 10);
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:= Address(15 downto 10);
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alias Comp_Addr is Bus_Address(15 downto 10);
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alias Comp_Addr is Bus_Address(15 downto 10);
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alias RAM_Addr is Bus_Address(9 downto 0);
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alias RAM_Addr is Bus_Address(9 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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signal Rd_Data_i : DATA_TYPE;
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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begin
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begin
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- do the lookup before we have to set Rd_Data
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-- do the lookup before we have to set Rd_Data
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| Line 80... |
Line 80... |
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Rd_Data_i;
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Rd_Data <= Rd_Data_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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