| Line 39... |
Line 39... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE
|
Rd_Data : out DATA_TYPE
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_ram_1k is
|
architecture behave of o8_ram_1k is
|
|
|
constant User_Addr : std_logic_vector(15 downto 10)
|
constant User_Addr : std_logic_vector(15 downto 10)
|
:= Address(15 downto 10);
|
:= Address(15 downto 10);
|
alias Comp_Addr is Bus_Address(15 downto 10);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 10);
|
alias RAM_Addr is Bus_Address(9 downto 0);
|
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
|
|
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
|
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
|
| Line 64... |
Line 61... |
begin
|
begin
|
|
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- do the lookup before we have to set Rd_Data
|
-- do the lookup before we have to set Rd_Data
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
|
|
-- Note that this RAM should be created without an output FF (unregistered Q)
|
-- Note that this RAM should be created without an output FF (unregistered Q)
|
U_RAM : entity work.ram_1k_core
|
U_RAM : entity work.ram_1k_core
|
port map(
|
port map(
|
address => RAM_Addr,
|
address => RAM_Addr,
|
clock => Clock,
|
clock => Clock,
|
data => Wr_Data,
|
data => Open8_Bus.Wr_Data,
|
wren => Wr_En,
|
wren => Wr_En,
|
q => Rd_Data_i
|
q => Rd_Data_i
|
);
|
);
|
|
|
RAM_proc: process( Reset, Clock )
|
RAM_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= Rd_Data_i;
|
Rd_Data <= Rd_Data_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
