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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_ram_1k
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-- VHDL Units : o8_ram_1k
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-- Description: Provides a wrapper layer for a 1kx8 RAM model
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-- Description: Provides a wrapper layer for a 1kx8 RAM model
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_ram_1k is
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entity o8_ram_1k is
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generic(
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generic(
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE
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Rd_Data : out DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_ram_1k is
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architecture behave of o8_ram_1k is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 10)
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constant User_Addr : std_logic_vector(15 downto 10)
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:= Address(15 downto 10);
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:= Address(15 downto 10);
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alias Comp_Addr is Open8_Bus.Address(15 downto 10);
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alias Comp_Addr is Open8_Bus.Address(15 downto 10);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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