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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_ram_1k
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-- VHDL Units : o8_ram_1k
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-- Description: Provides a wrapper layer for a 1kx8 RAM model
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-- Description: Provides a wrapper layer for a 1kx8 RAM model with interface
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-- : logic for the Open8 CPU. Also provides an optional write
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-- : enable register that prevents regions from being written
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-- : by non-ISR code (uses the I flag) as a way to prevent tasks
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-- : from inadvertently writing outside of their designated
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-- : memory space.
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-- : When enabled, the write mask logically divides the memory into
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-- : 16, 64 byte regions, corresponding to the 16 bits in the WPR
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-- : register.
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--
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-- WP Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
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-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 05/12/20 Added write protect logic
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_ram_1k is
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entity o8_ram_1k is
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generic(
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generic(
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Address : ADDRESS_TYPE
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Write_Protect : boolean := FALSE;
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Default_Mask : ADDRESS_TYPE := x"0000";
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Address_WPR : ADDRESS_TYPE := x"0400";
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Address_RAM : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE
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Rd_Data : out DATA_TYPE
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);
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);
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architecture behave of o8_ram_1k is
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architecture behave of o8_ram_1k is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
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alias Wr_En is Open8_Bus.Wr_En;
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alias Rd_En is Open8_Bus.Rd_En;
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constant WPR_User_Addr : std_logic_vector(15 downto 1)
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:= Address_WPR(15 downto 1);
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constant RAM_User_Addr : std_logic_vector(15 downto 10)
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:= Address_RAM(15 downto 10);
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alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
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signal WPR_Addr_Match : std_logic := '0';
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alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
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signal WPR_Reg_Sel : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data : DATA_TYPE := x"00";
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constant User_Addr : std_logic_vector(15 downto 10)
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signal Write_Mask : std_logic_vector(15 downto 0) :=
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:= Address(15 downto 10);
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x"0000";
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alias Comp_Addr is Open8_Bus.Address(15 downto 10);
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alias Write_Mask_0 is Write_Mask(7 downto 0);
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alias Write_Mask_1 is Write_Mask(15 downto 8);
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signal WPR_Wr_En : std_logic := '0';
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signal WPR_Rd_En : std_logic := '0';
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alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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signal Addr_Match : std_logic := '0';
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alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
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signal Wr_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal RAM_Region_Match : std_logic := '0';
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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begin
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begin
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-- This decode needs to happen immediately, to give the RAM a chance to
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Write_Protect_On : if( Write_Protect )generate
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-- do the lookup before we have to set Rd_Data
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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-- Note that this RAM should be created without an output FF (unregistered Q)
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WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
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U_RAM : entity work.ram_1k_core
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port map(
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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address => RAM_Addr,
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clock => Clock,
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RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
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data => Open8_Bus.Wr_Data,
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ISR_En;
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wren => Wr_En,
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q => Rd_Data_i
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RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
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);
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RAM_proc: process( Reset, Clock )
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begin
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if( Reset = Reset_Level )then
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Write_Mask <= Default_Mask;
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WPR_Reg_Sel <= '0';
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WPR_Wr_En <= '0';
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WPR_Rd_En <= '0';
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RAM_Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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WPR_Reg_Sel <= WPR_Reg_Sel_d;
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WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
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Wr_Data <= Wr_Data_d;
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if( WPR_Wr_En = '1' )then
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case( WPR_Reg_Sel )is
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when '0' =>
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Write_Mask_0 <= Wr_Data;
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when '1' =>
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Write_Mask_1 <= Wr_Data;
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when others =>
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null;
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end case;
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end if;
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WPR_Rd_En <= WPR_Addr_Match and Rd_En;
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RAM_Rd_En <= RAM_Addr_Match and Rd_En;
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Rd_Data <= OPEN8_NULLBUS;
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if( WPR_Rd_En = '1' )then
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case( WPR_Reg_Sel )is
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when '0' =>
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Rd_Data <= Write_Mask_0;
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when '1' =>
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Rd_Data <= Write_Mask_1;
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when others =>
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null;
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end case;
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end if;
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if( RAM_Rd_En = '1' )then
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Rd_Data <= RAM_Rd_Data;
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end if;
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end if;
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end process;
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end generate;
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Write_Protect_Off : if( not Write_Protect )generate
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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RAM_Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( RAM_Rd_En = '1' )then
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Rd_Data <= Rd_Data_i;
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Rd_Data <= RAM_Rd_Data;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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-- Note that this RAM should be created without an output FF (unregistered Q)
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U_RAM : entity work.ram_1k_core
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port map(
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address => RAM_Addr,
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clock => Clock,
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data => Wr_Data_d,
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wren => RAM_Wr_En,
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q => RAM_Rd_Data
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);
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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