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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_1k.vhd] - Diff between revs 243 and 244

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Rev 243 Rev 244
Line 80... Line 80...
 
 
  alias  WPR_Comp_Addr       is Open8_Bus.Address(15 downto 1);
  alias  WPR_Comp_Addr       is Open8_Bus.Address(15 downto 1);
  signal WPR_Addr_Match      : std_logic := '0';
  signal WPR_Addr_Match      : std_logic := '0';
 
 
  alias  WPR_Reg_Sel_d       is Open8_Bus.Address(0);
  alias  WPR_Reg_Sel_d       is Open8_Bus.Address(0);
  signal WPR_Reg_Sel         : std_logic := '0';
  signal WPR_Reg_Sel_q       : std_logic := '0';
 
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  signal Wr_Data             : DATA_TYPE := x"00";
  signal WPR_Wr_Data_q       : DATA_TYPE := x"00";
 
 
  signal Write_Mask          : std_logic_vector(15 downto 0) :=
  signal Write_Mask          : std_logic_vector(15 downto 0) :=
                                x"0000";
                                x"0000";
  alias  Write_Mask_0        is Write_Mask(7 downto 0);
  alias  Write_Mask_0        is Write_Mask(7 downto 0);
  alias  Write_Mask_1        is Write_Mask(15 downto 8);
  alias  Write_Mask_1        is Write_Mask(15 downto 8);
 
 
  signal WPR_Wr_En           : std_logic := '0';
  signal WPR_Wr_En_d         : std_logic := '0';
  signal WPR_Rd_En           : std_logic := '0';
  signal WPR_Wr_En_q         : std_logic := '0';
 
  signal WPR_Rd_En_d         : std_logic := '0';
 
  signal WPR_Rd_En_q         : std_logic := '0';
 
 
  alias  RAM_Base_Addr       is Open8_Bus.Address(15 downto 10);
  alias  RAM_Base_Addr       is Open8_Bus.Address(15 downto 10);
  alias  RAM_Addr            is Open8_Bus.Address(9 downto 0);
  alias  RAM_Addr            is Open8_Bus.Address(9 downto 0);
 
 
  alias  RAM_Rgn_Addr        is Open8_Bus.Address(9 downto 6);
  alias  RAM_Rgn_Addr        is Open8_Bus.Address(9 downto 6);
 
 
  signal RAM_Region_Match    : std_logic := '0';
  signal RAM_Region_Match    : std_logic := '0';
  signal RAM_Addr_Match      : std_logic := '0';
  signal RAM_Addr_Match      : std_logic := '0';
 
 
  signal RAM_Wr_En           : std_logic := '0';
  signal RAM_Wr_En_d         : std_logic := '0';
  signal RAM_Rd_En           : std_logic := '0';
  signal RAM_Rd_En_d         : std_logic := '0';
 
  signal RAM_Rd_En_q         : std_logic := '0';
  signal RAM_Rd_Data         : DATA_TYPE := OPEN8_NULLBUS;
  signal RAM_Rd_Data         : DATA_TYPE := OPEN8_NULLBUS;
 
 
begin
begin
 
 
Write_Protect_On : if( Write_Protect )generate
Write_Protect_On : if( Write_Protect )generate
 
 
  WPR_Addr_Match             <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
  WPR_Addr_Match             <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
 
  WPR_Wr_En_d                <= WPR_Addr_Match and Wr_En and ISR_En;
 
  WPR_Rd_En_d                <= WPR_Addr_Match and Rd_En;
 
 
  RAM_Addr_Match             <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
  RAM_Addr_Match             <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
 
  RAM_Region_Match           <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
  RAM_Region_Match           <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
                                ISR_En;
                                ISR_En;
 
 
  RAM_Wr_En                  <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
  RAM_Rd_En_d                <= RAM_Addr_Match and Rd_En;
 
  RAM_Wr_En_d                <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
 
  RAM_proc: process( Reset, Clock )
  RAM_proc: process( Reset, Clock )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Write_Mask             <= Default_Mask;
      WPR_Reg_Sel_q          <= '0';
 
      WPR_Wr_Data_q          <= x"00";
 
 
      WPR_Reg_Sel            <= '0';
      WPR_Wr_En_q            <= '0';
 
      WPR_Rd_En_q            <= '0';
 
 
      WPR_Wr_En              <= '0';
      Write_Mask             <= Default_Mask;
      WPR_Rd_En              <= '0';
 
 
 
      RAM_Rd_En              <= '0';
      RAM_Rd_En_q            <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      WPR_Reg_Sel            <= WPR_Reg_Sel_d;
      WPR_Reg_Sel_q          <= WPR_Reg_Sel_d;
 
 
      WPR_Wr_En              <= WPR_Addr_Match and Wr_En and ISR_En;
      WPR_Wr_En_q            <= WPR_Wr_En_d;
      Wr_Data                <= Wr_Data_d;
      WPR_Wr_Data_q          <= Wr_Data_d;
      if( WPR_Wr_En = '1' )then
      if( WPR_Wr_En_q = '1' )then
        case( WPR_Reg_Sel )is
        case( WPR_Reg_Sel_q )is
          when '0' =>
          when '0' =>
            Write_Mask_0     <= Wr_Data;
            Write_Mask_0     <= WPR_Wr_Data_q;
          when '1' =>
          when '1' =>
            Write_Mask_1     <= Wr_Data;
            Write_Mask_1     <= WPR_Wr_Data_q;
          when others =>
          when others =>
            null;
            null;
        end case;
        end case;
      end if;
      end if;
 
 
      WPR_Rd_En              <= WPR_Addr_Match and Rd_En;
      WPR_Rd_En_q            <= WPR_Rd_En_d;
      RAM_Rd_En              <= RAM_Addr_Match and Rd_En;
      RAM_Rd_En_q            <= RAM_Rd_En_d;
 
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      if( RAM_Rd_En = '1' )then
      if( RAM_Rd_En_q = '1' )then
        Rd_Data              <= RAM_Rd_Data;
        Rd_Data              <= RAM_Rd_Data;
      elsif( WPR_Rd_En = '1'  )then
      elsif( WPR_Rd_En_q = '1'  )then
        case( WPR_Reg_Sel )is
        case( WPR_Reg_Sel_q )is
          when '0' =>
          when '0' =>
            Rd_Data          <= Write_Mask_0;
            Rd_Data          <= Write_Mask_0;
          when '1' =>
          when '1' =>
            Rd_Data          <= Write_Mask_1;
            Rd_Data          <= Write_Mask_1;
          when others =>
          when others =>
Line 171... Line 178...
 
 
Write_Protect_Off : if( not Write_Protect )generate
Write_Protect_Off : if( not Write_Protect )generate
 
 
  RAM_Addr_Match             <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
  RAM_Addr_Match             <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
 
  RAM_Wr_En                  <= RAM_Addr_Match and Open8_Bus.Wr_En;
  RAM_Rd_En_d                <= RAM_Addr_Match and Open8_Bus.Rd_En;
 
  RAM_Wr_En_d                <= RAM_Addr_Match and Open8_Bus.Wr_En;
 
 
  RAM_proc: process( Reset, Clock )
  RAM_proc: process( Reset, Clock )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      RAM_Rd_En              <= '0';
      RAM_Rd_En_q            <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      RAM_Rd_En              <= RAM_Addr_Match and Open8_Bus.Rd_En;
      RAM_Rd_En_q            <= RAM_Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      if( RAM_Rd_En = '1' )then
      if( RAM_Rd_En_q = '1' )then
        Rd_Data              <= RAM_Rd_Data;
        Rd_Data              <= RAM_Rd_Data;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
Line 195... Line 203...
  U_RAM : entity work.ram_1k_core
  U_RAM : entity work.ram_1k_core
  port map(
  port map(
    address                  => RAM_Addr,
    address                  => RAM_Addr,
    clock                    => Clock,
    clock                    => Clock,
    data                     => Wr_Data_d,
    data                     => Wr_Data_d,
    wren                     => RAM_Wr_En,
    wren                     => RAM_Wr_En_d,
    q                        => RAM_Rd_Data
    q                        => RAM_Rd_Data
  );
  );
 
 
end architecture;
end architecture;
 
 
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