| Line 80... |
Line 80... |
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alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
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signal WPR_Addr_Match : std_logic := '0';
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signal WPR_Addr_Match : std_logic := '0';
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alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
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alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
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signal WPR_Reg_Sel : std_logic := '0';
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signal WPR_Reg_Sel_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data : DATA_TYPE := x"00";
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signal WPR_Wr_Data_q : DATA_TYPE := x"00";
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signal Write_Mask : std_logic_vector(15 downto 0) :=
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signal Write_Mask : std_logic_vector(15 downto 0) :=
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x"0000";
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x"0000";
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alias Write_Mask_0 is Write_Mask(7 downto 0);
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alias Write_Mask_0 is Write_Mask(7 downto 0);
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alias Write_Mask_1 is Write_Mask(15 downto 8);
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alias Write_Mask_1 is Write_Mask(15 downto 8);
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signal WPR_Wr_En : std_logic := '0';
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signal WPR_Wr_En_d : std_logic := '0';
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signal WPR_Rd_En : std_logic := '0';
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signal WPR_Wr_En_q : std_logic := '0';
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signal WPR_Rd_En_d : std_logic := '0';
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signal WPR_Rd_En_q : std_logic := '0';
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alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
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alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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alias RAM_Addr is Open8_Bus.Address(9 downto 0);
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alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
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alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
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signal RAM_Region_Match : std_logic := '0';
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signal RAM_Region_Match : std_logic := '0';
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Wr_En_d : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal RAM_Rd_En_d : std_logic := '0';
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signal RAM_Rd_En_q : std_logic := '0';
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signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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begin
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begin
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Write_Protect_On : if( Write_Protect )generate
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Write_Protect_On : if( Write_Protect )generate
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WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
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WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
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WPR_Wr_En_d <= WPR_Addr_Match and Wr_En and ISR_En;
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WPR_Rd_En_d <= WPR_Addr_Match and Rd_En;
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
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RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
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ISR_En;
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ISR_En;
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RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
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RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
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RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Write_Mask <= Default_Mask;
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WPR_Reg_Sel_q <= '0';
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WPR_Wr_Data_q <= x"00";
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WPR_Reg_Sel <= '0';
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WPR_Wr_En_q <= '0';
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WPR_Rd_En_q <= '0';
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WPR_Wr_En <= '0';
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Write_Mask <= Default_Mask;
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WPR_Rd_En <= '0';
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RAM_Rd_En <= '0';
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RAM_Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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WPR_Reg_Sel <= WPR_Reg_Sel_d;
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WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
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WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
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WPR_Wr_En_q <= WPR_Wr_En_d;
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Wr_Data <= Wr_Data_d;
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WPR_Wr_Data_q <= Wr_Data_d;
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if( WPR_Wr_En = '1' )then
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if( WPR_Wr_En_q = '1' )then
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case( WPR_Reg_Sel )is
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case( WPR_Reg_Sel_q )is
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when '0' =>
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when '0' =>
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Write_Mask_0 <= Wr_Data;
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Write_Mask_0 <= WPR_Wr_Data_q;
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when '1' =>
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when '1' =>
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Write_Mask_1 <= Wr_Data;
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Write_Mask_1 <= WPR_Wr_Data_q;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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WPR_Rd_En <= WPR_Addr_Match and Rd_En;
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WPR_Rd_En_q <= WPR_Rd_En_d;
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RAM_Rd_En <= RAM_Addr_Match and Rd_En;
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RAM_Rd_En_q <= RAM_Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( RAM_Rd_En = '1' )then
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if( RAM_Rd_En_q = '1' )then
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Rd_Data <= RAM_Rd_Data;
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Rd_Data <= RAM_Rd_Data;
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elsif( WPR_Rd_En = '1' )then
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elsif( WPR_Rd_En_q = '1' )then
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case( WPR_Reg_Sel )is
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case( WPR_Reg_Sel_q )is
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when '0' =>
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when '0' =>
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Rd_Data <= Write_Mask_0;
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Rd_Data <= Write_Mask_0;
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when '1' =>
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when '1' =>
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Rd_Data <= Write_Mask_1;
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Rd_Data <= Write_Mask_1;
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when others =>
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when others =>
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| Line 171... |
Line 178... |
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Write_Protect_Off : if( not Write_Protect )generate
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Write_Protect_Off : if( not Write_Protect )generate
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
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RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
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RAM_Rd_En_d <= RAM_Addr_Match and Open8_Bus.Rd_En;
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RAM_Wr_En_d <= RAM_Addr_Match and Open8_Bus.Wr_En;
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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RAM_Rd_En <= '0';
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RAM_Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
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RAM_Rd_En_q <= RAM_Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( RAM_Rd_En = '1' )then
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if( RAM_Rd_En_q = '1' )then
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Rd_Data <= RAM_Rd_Data;
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Rd_Data <= RAM_Rd_Data;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 195... |
Line 203... |
U_RAM : entity work.ram_1k_core
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U_RAM : entity work.ram_1k_core
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port map(
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port map(
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address => RAM_Addr,
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address => RAM_Addr,
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clock => Clock,
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clock => Clock,
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data => Wr_Data_d,
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data => Wr_Data_d,
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wren => RAM_Wr_En,
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wren => RAM_Wr_En_d,
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q => RAM_Rd_Data
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q => RAM_Rd_Data
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);
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);
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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