| Line 27... |
Line 27... |
-- : enable register that prevents regions from being written
|
-- : enable register that prevents regions from being written
|
-- : by non-ISR code (uses the I flag) as a way to prevent tasks
|
-- : by non-ISR code (uses the I flag) as a way to prevent tasks
|
-- : from inadvertently writing outside of their designated
|
-- : from inadvertently writing outside of their designated
|
-- : memory space.
|
-- : memory space.
|
-- : When enabled, the write mask logically divides the memory into
|
-- : When enabled, the write mask logically divides the memory into
|
-- : 16, 64 byte regions, corresponding to the 16 bits in the WPR
|
-- : 32, 32-byte regions, corresponding to the 32 bits in the WPR
|
-- : register.
|
-- : register.
|
--
|
--
|
-- WP Register Map:
|
-- WP Register Map:
|
-- Offset Bitfield Description Read/Write
|
-- Offset Bitfield Description Read/Write
|
-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
|
-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
|
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
|
-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
|
|
-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
|
|
-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
|
|
-- 0x04 AAAAAAAA Fault Address 7:0 (RW*)
|
|
-- 0x05 AAAAAAAA Fault Address 15:8 (RW*)
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 04/16/20 Revision block added
|
-- Seth Henry 04/16/20 Revision block added
|
-- Seth Henry 05/12/20 Added write protect logic
|
-- Seth Henry 05/12/20 Added write protect logic
|
|
-- Seth Henry 10/04/23 Modified WPR to match 4K RAM and added fault
|
|
-- address capture
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 52... |
Line 58... |
use work.open8_pkg.all;
|
use work.open8_pkg.all;
|
|
|
entity o8_ram_1k is
|
entity o8_ram_1k is
|
generic(
|
generic(
|
Write_Protect : boolean := FALSE;
|
Write_Protect : boolean := FALSE;
|
Default_Mask : ADDRESS_TYPE := x"0000";
|
Default_Mask : std_logic_vector(31 downto 0) := x"00000000";
|
Address_WPR : ADDRESS_TYPE := x"0400";
|
Address_WPR : ADDRESS_TYPE := x"0400";
|
Address_RAM : ADDRESS_TYPE
|
Address_RAM : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
| Line 68... |
Line 74... |
architecture behave of o8_ram_1k is
|
architecture behave of o8_ram_1k is
|
|
|
alias Clock is Open8_Bus.Clock;
|
alias Clock is Open8_Bus.Clock;
|
alias Reset is Open8_Bus.Reset;
|
alias Reset is Open8_Bus.Reset;
|
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
|
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
|
|
alias Full_Address is Open8_Bus.Address;
|
alias Wr_En is Open8_Bus.Wr_En;
|
alias Wr_En is Open8_Bus.Wr_En;
|
alias Rd_En is Open8_Bus.Rd_En;
|
alias Rd_En is Open8_Bus.Rd_En;
|
|
|
constant WPR_User_Addr : std_logic_vector(15 downto 1)
|
constant WPR_User_Addr : std_logic_vector(15 downto 3)
|
:= Address_WPR(15 downto 1);
|
:= Address_WPR(15 downto 3);
|
|
|
constant RAM_User_Addr : std_logic_vector(15 downto 10)
|
constant RAM_User_Addr : std_logic_vector(15 downto 10)
|
:= Address_RAM(15 downto 10);
|
:= Address_RAM(15 downto 10);
|
|
|
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 1);
|
alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 3);
|
signal WPR_Addr_Match : std_logic := '0';
|
signal WPR_Addr_Match : std_logic := '0';
|
|
|
alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
|
alias WPR_Reg_Sel_d is Open8_Bus.Address(2 downto 0);
|
signal WPR_Reg_Sel_q : std_logic := '0';
|
signal WPR_Reg_Sel_q : std_logic_vector(2 downto 0) :=
|
|
(others => '0');
|
|
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
signal WPR_Wr_Data_q : DATA_TYPE := x"00";
|
signal WPR_Wr_Data_q : DATA_TYPE := x"00";
|
|
|
signal Write_Mask : std_logic_vector(15 downto 0) :=
|
signal Write_Mask : std_logic_vector(31 downto 0) :=
|
x"0000";
|
x"00000000";
|
alias Write_Mask_0 is Write_Mask(7 downto 0);
|
alias Write_Mask_0 is Write_Mask(7 downto 0);
|
alias Write_Mask_1 is Write_Mask(15 downto 8);
|
alias Write_Mask_1 is Write_Mask(15 downto 8);
|
|
alias Write_Mask_2 is Write_Mask(23 downto 16);
|
|
alias Write_Mask_3 is Write_Mask(31 downto 24);
|
|
|
signal WPR_Wr_En_d : std_logic := '0';
|
signal WPR_Wr_En_d : std_logic := '0';
|
signal WPR_Wr_En_q : std_logic := '0';
|
signal WPR_Wr_En_q : std_logic := '0';
|
signal WPR_Rd_En_d : std_logic := '0';
|
signal WPR_Rd_En_d : std_logic := '0';
|
signal WPR_Rd_En_q : std_logic := '0';
|
signal WPR_Rd_En_q : std_logic := '0';
|
|
|
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
|
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
|
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
|
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
|
|
|
alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 6);
|
alias RAM_Rgn_Addr is Open8_Bus.Address(9 downto 5);
|
|
|
signal RAM_Region_Match : std_logic := '0';
|
signal RAM_Region_Match : std_logic := '0';
|
signal RAM_Addr_Match : std_logic := '0';
|
signal RAM_Addr_Match : std_logic := '0';
|
|
|
signal RAM_Wr_En_d : std_logic := '0';
|
signal RAM_Wr_En_d : std_logic := '0';
|
signal RAM_Rd_En_d : std_logic := '0';
|
signal RAM_Rd_En_d : std_logic := '0';
|
signal RAM_Rd_En_q : std_logic := '0';
|
signal RAM_Rd_En_q : std_logic := '0';
|
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
|
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
|
|
|
signal Write_Fault_d : std_logic := '0';
|
signal Write_Fault_d : std_logic := '0';
|
|
signal Write_Fault_q : std_logic := '0';
|
|
|
|
signal Current_Addr : ADDRESS_TYPE := x"0000";
|
|
signal Fault_Addr : ADDRESS_TYPE := x"0000";
|
|
alias Fault_Addr_l is Fault_Addr(7 downto 0);
|
|
alias Fault_Addr_h is Fault_Addr(15 downto 8);
|
|
|
begin
|
begin
|
|
|
Write_Protect_On : if( Write_Protect )generate
|
Write_Protect_On : if( Write_Protect )generate
|
|
|
| Line 129... |
Line 145... |
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
|
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
|
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
|
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
|
|
|
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
|
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
|
|
|
|
Write_Fault <= Write_Fault_q;
|
|
|
RAM_proc: process( Reset, Clock )
|
RAM_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
WPR_Reg_Sel_q <= '0';
|
WPR_Reg_Sel_q <= (others => '0');
|
WPR_Wr_Data_q <= x"00";
|
WPR_Wr_Data_q <= x"00";
|
|
|
WPR_Wr_En_q <= '0';
|
WPR_Wr_En_q <= '0';
|
WPR_Rd_En_q <= '0';
|
WPR_Rd_En_q <= '0';
|
|
|
| Line 144... |
Line 162... |
|
|
RAM_Rd_En_q <= '0';
|
RAM_Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
Write_Fault <= '0';
|
Write_Fault <= '0';
|
|
Current_Addr <= x"0000";
|
|
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
|
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
|
|
|
WPR_Wr_En_q <= WPR_Wr_En_d;
|
WPR_Wr_En_q <= WPR_Wr_En_d;
|
WPR_Wr_Data_q <= Wr_Data_d;
|
WPR_Wr_Data_q <= Wr_Data_d;
|
if( WPR_Wr_En_q = '1' )then
|
if( WPR_Wr_En_q = '1' )then
|
case( WPR_Reg_Sel_q )is
|
case( WPR_Reg_Sel_q )is
|
when '0' =>
|
when "000" =>
|
Write_Mask_0 <= WPR_Wr_Data_q;
|
Write_Mask_0 <= WPR_Wr_Data_q;
|
when '1' =>
|
when "001" =>
|
Write_Mask_1 <= WPR_Wr_Data_q;
|
Write_Mask_1 <= WPR_Wr_Data_q;
|
|
when "010" =>
|
|
Write_Mask_2 <= WPR_Wr_Data_q;
|
|
when "011" =>
|
|
Write_Mask_3 <= WPR_Wr_Data_q;
|
|
when "100" | "101" =>
|
|
Fault_Addr <= (others => '0');
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
| Line 169... |
Line 194... |
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( RAM_Rd_En_q = '1' )then
|
if( RAM_Rd_En_q = '1' )then
|
Rd_Data <= RAM_Rd_Data;
|
Rd_Data <= RAM_Rd_Data;
|
elsif( WPR_Rd_En_q = '1' )then
|
elsif( WPR_Rd_En_q = '1' )then
|
case( WPR_Reg_Sel_q )is
|
case( WPR_Reg_Sel_q )is
|
when '0' =>
|
when "000" =>
|
Rd_Data <= Write_Mask_0;
|
Rd_Data <= Write_Mask_0;
|
when '1' =>
|
when "001" =>
|
Rd_Data <= Write_Mask_1;
|
Rd_Data <= Write_Mask_1;
|
|
when "010" =>
|
|
Rd_Data <= Write_Mask_2;
|
|
when "011" =>
|
|
Rd_Data <= Write_Mask_3;
|
|
when "100" =>
|
|
Rd_Data <= Fault_Addr_l;
|
|
when "101" =>
|
|
Rd_Data <= Fault_Addr_h;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Write_Fault <= Write_Fault_d;
|
Write_Fault_q <= Write_Fault_d;
|
|
|
|
Current_Addr <= Full_Address;
|
|
if( Write_Fault_q = '1' )then
|
|
Fault_Addr <= Current_Addr;
|
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end generate;
|
end generate;
|
