URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_4k.vhd] - Diff between revs 242 and 243

Rev 242	Rev 243
Line 159...	Line 159...
`end case;`	`end case;`
`end if;`	`end if;`

`WPR_Rd_En <= WPR_Addr_Match and Rd_En;`	`WPR_Rd_En <= WPR_Addr_Match and Rd_En;`
`RAM_Rd_En <= RAM_Addr_Match and Rd_En;`	`RAM_Rd_En <= RAM_Addr_Match and Rd_En;`

`Rd_Data <= OPEN8_NULLBUS;`	`Rd_Data <= OPEN8_NULLBUS;`
`if( WPR_Rd_En = '1' )then`	`if( RAM_Rd_En = '1' )then`
	`Rd_Data <= RAM_Rd_Data;`
	`elsif( WPR_Rd_En = '1' )then`
`case( WPR_Reg_Sel )is`	`case( WPR_Reg_Sel )is`
`when "00" =>`	`when "00" =>`
`Rd_Data <= Write_Mask_0;`	`Rd_Data <= Write_Mask_0;`
`when "01" =>`	`when "01" =>`
`Rd_Data <= Write_Mask_1;`	`Rd_Data <= Write_Mask_1;`
Line 174...	Line 177...
`Rd_Data <= Write_Mask_3;`	`Rd_Data <= Write_Mask_3;`
`when others =>`	`when others =>`
`null;`	`null;`
`end case;`	`end case;`
`end if;`	`end if;`
`if( RAM_Rd_En = '1' )then`
`Rd_Data <= RAM_Rd_Data;`
`end if;`
`end if;`	`end if;`
`end process;`	`end process;`

`end generate;`	`end generate;`